On Tue, Oct 08, 2024 at 01:34:56PM -0500, Lucas De Marchi wrote:
v2 of my attempt at fixing how i915 interacts with perf events.
v1 -
https://lore.kernel.org/all/20240722210648.80892-1-lucas.demar...@intel.com/
From other people:
1)
https://lore.kernel.org/lkml/20240115170120.662220-1-tvrtko.
On Thu, May 16, 2024 at 02:52:01PM -0500, Lucas De Marchi wrote:
On Thu, May 16, 2024 at 11:33:54AM GMT, Umesh Nerlige Ramappa wrote:
On Wed, May 15, 2024 at 02:42:56PM -0700, Lucas De Marchi wrote:
gt->info.engine_mask used to indicate the available engines, but that
is not always t
ds in tools like gputop (from
igt), htop, nvtop, etc, with none of them really defaulting to 1 sample
per minute or more.
Signed-off-by: Lucas De Marchi
LGTM,
Reviewed-by: Umesh Nerlige Ramappa
Thanks,
Umesh
---
Documentation/gpu/drm-usage-stats.rst | 21 +++-
Documentation/gpu/xe/inde
On Wed, May 15, 2024 at 02:42:57PM -0700, Lucas De Marchi wrote:
Get the first available engine from a gt, which helps in the case any
engine serves as a context, like when reading RING_TIMESTAMP.
Signed-off-by: Lucas De Marchi
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/xe
rchi
Just a few questions below, otherwise this looks good as is:
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/xe/xe_gt.c | 23 +++
drivers/gpu/drm/xe/xe_gt.h | 13 +
drivers/gpu/drm/xe/xe_gt_ccs_mode.c | 1 +
drivers/gpu/drm/xe/xe_
On Tue, May 07, 2024 at 03:45:10PM -0700, Lucas De Marchi wrote:
Print the accumulated runtime for client when printing fdinfo.
Each time a query is done it first does 2 things:
1) loop through all the exec queues for the current client and
accumulate the runtime, per engine class. CTX_TIMESTA
On Tue, May 07, 2024 at 03:45:09PM -0700, Lucas De Marchi wrote:
From: Umesh Nerlige Ramappa
Add a helper to accumulate per-client runtime of all its
exec queues. This is called every time a sched job is finished.
v2:
- Use guc_exec_queue_free_job() and execlist_job_free() to accumulate
On Fri, Apr 26, 2024 at 11:49:32AM +0100, Tvrtko Ursulin wrote:
On 24/04/2024 00:56, Lucas De Marchi wrote:
From: Umesh Nerlige Ramappa
Add a helper to accumulate per-client runtime of all its
exec queues. Currently that is done in 2 places:
1. when the exec_queue is destroyed
On Fri, Sep 22, 2023 at 03:25:08PM -0700, john.c.harri...@intel.com wrote:
From: John Harrison
The GuC has been extended to support a much more friendly engine
busyness interface. So partition the old interface into a 'busy_v1'
space and add 'busy_v2' support alongside. And if v2 is available,
On Mon, Sep 25, 2023 at 09:40:46AM +0100, Tvrtko Ursulin wrote:
On 22/09/2023 23:25, john.c.harri...@intel.com wrote:
From: Umesh Nerlige Ramappa
Current engine busyness interface exposed by GuC has a few issues:
- The busyness of active engine is calculated using 2 values provided by
GuC
On Mon, May 22, 2023 at 02:50:51PM -0700, Dixit, Ashutosh wrote:
On Mon, 22 May 2023 14:34:18 -0700, Umesh Nerlige Ramappa wrote:
On Mon, May 22, 2023 at 01:17:49PM -0700, Ashutosh Dixit wrote:
> Clearing out report id and timestamp as means to detect unlanded reports
> only works if
same place each time in the OA buffer (after rewind). If report
size is not a power of 2, we need to zero out the entire report to be able
to detect unlanded reports reliably.
Cc: Umesh Nerlige Ramappa
Signed-off-by: Ashutosh Dixit
---
drivers/gpu/drm/i915/i915_perf.c | 17 +++--
1
On Tue, May 16, 2023 at 03:13:01PM -0700, Umesh Nerlige Ramappa wrote:
On Tue, May 16, 2023 at 10:24:45AM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Having it as u64 was a confusing (but harmless) mistake.
Also add some asserts to make sure the internal field does not overflow
in the
Nerlige Ramappa
---
I am not entirely sure the __builtin_constant_p->BUILD_BUG_ON branch will
work with all compilers. Lets see...
Compile tested only.
---
drivers/gpu/drm/i915/i915_pmu.c | 32 ++--
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/driv
that reason, unlocking the
metrics_lock must be done after we are done dereferencing the object.
Signed-off-by: Min Li
Fixes: f89823c21224 ("drm/i915/perf: Implement I915_PERF_ADD/REMOVE_CONFIG
interface")
Cc: Lionel Landwerlin
Cc: Umesh Nerlige Ramappa
Cc: # v4.14+
---
drivers/gp
On Tue, Nov 29, 2022 at 01:12:53PM -0800, john.c.harri...@intel.com wrote:
From: John Harrison
Engine resets are supposed to never happen. But in the case when one
does (due to unknwon reasons that normally come down to a missing
w/a), it is useful to get as much information out of the system a
15_request_get_rcu(rq);
- if (!rq)
- goto no_request_capture;
+ if (rq)
+ capture = intel_engine_coredump_add_request(ee, rq,
ATOMIC_MAYFAIL);
2 back-to-back if (rq) could merge together,
otherwise, lgtm
Reviewed-by: Umesh Ne
. Given that
the extra line feeds are just in the middle of random bits of GuC
state, there isn't any real need for them. So just remove them
completely.
Signed-off-by: John Harrison
lgtm,
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/uc/intel_guc.c| 4 ++--
dr
is
performing the same activities that the ping-worker would do if it were
to run, so we should be safe to skip the worker when a reset is in
progress, so lgtm,
Reviewed-by: Umesh Nerlige Ramappa
Thanks,
Umesh
John.
Regards,
Tvrtko
On Fri, Oct 21, 2022 at 09:42:53AM +0100, Tvrtko Ursulin wrote:
On 27/10/2021 01:48, Umesh Nerlige Ramappa wrote:
[snip]
+static void guc_timestamp_ping(struct work_struct *wrk)
+{
+ struct intel_guc *guc = container_of(wrk, typeof(*guc
idle even if there are contexts from apps Y, Z, ... waiting to run. A
certain OS favours RCS to the total starvation of CCS. Linux does not.
Hence the GuC now has a scheduling policy setting to control this
abitration.
Signed-off-by: John Harrison
lgtm,
Reviewed-by: Umesh Nerlige Ramappa
On Wed, Jun 15, 2022 at 04:27:36PM +0100, Mauro Carvalho Chehab wrote:
From: Chris Wilson
On gen12 HW, ensure that the TLB of the OA unit is also invalidated
as just invalidating the TLB of an engine is not enough.
Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
Si
lgtm, thanks for clarifications on the other patch.
Reviewed-by: Umesh Nerlige Ramappa
Umesh
On Fri, Apr 01, 2022 at 03:11:53PM +0100, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Tests and intel_gpu_top will share common code for parsing this file.
v2:
* Fix key-value parsing if valid key
lgtm, I just have a few nits and questions below:
Regardless, this is
Reviewed-by: Umesh Nerlige Ramappa
Umesh
On Tue, Feb 22, 2022 at 01:55:57PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Use the i915 exported data in /proc//fdinfo to show GPU utilization
per DRM client.
Example
This looks very similar to existing perf_pmu tests with the slight
change that the busyness is now captured from the fdinfo.
lgtm,
Reviewed-by: Umesh Nerlige Ramappa
Umesh
On Tue, Feb 22, 2022 at 01:55:56PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Mostly inherited from the
On Tue, Feb 22, 2022 at 01:55:55PM +, Tvrtko Ursulin wrote:
From: Tvrtko Ursulin
Tests and intel_gpu_top will share common code for parsing this file.
Signed-off-by: Tvrtko Ursulin
---
lib/igt_drm_fdinfo.c | 183 +++
lib/igt_drm_fdinfo.h | 48 ++
guc_resume and execlist_resume call
xehp_enable_ccs_engines(engine) for render case?
Also what happens if render itself is not present/fused-off (if there is
such a thing)?
Just those questions, overall the patch looks fine as is:
Reviewed-by: Umesh Nerlige Ramappa
Umesh
}
static inline void guc_default_irqs(struct intel_engine_cs *engine)
--
2.34.1
iver implements the DRM client usage stats specification as
+documented in :ref:`drm-client-usage-stats`.
+
+Example of the output showing the implemented key value pairs and entirety of
+the currenly possible format options:
s/currenly/currently/
lgtm, for the series
Reviewed-by: Umesh Nerlige Ramappa
Regards,
Umesh
On Tue, Feb 15, 2022 at 11:01:15AM +0530, Ramalingam C wrote:
i915_perf is not enabled for dg2 yet, hence skip the feature
initialization.
Signed-off-by: Ramalingam C
cc: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/i915_perf.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers
On Wed, Feb 16, 2022 at 10:15:04AM -0800, Vinay Belgaumkar wrote:
SLPC unset param H2G only needs one parameter - the id of the
param.
Fixes: 025cb07bebfa ("drm/i915/guc/slpc: Cache platform frequency limits")
Suggested-by: Umesh Nerlige Ramappa
Signed-off-by: Vinay Belgaumkar
-
On Mon, Jan 03, 2022 at 01:17:10PM -0800, Matt Roper wrote:
On Tue, Dec 21, 2021 at 09:46:29PM +0200, Andi Shyti wrote:
Hi Matt,
> > diff --git a/drivers/gpu/drm/i915/i915_perf.c
b/drivers/gpu/drm/i915/i915_perf.c
> > index 170bba913c30..128315aec517 100644
> > --- a/drivers/gpu/drm/i915/i915_
-
live_engine_busy_stats. For (1) the selftest waits until busyness stats
are visible to the CPU. The effects of (2) are more prominent for the
current busyness sample period of 100 us. Increase the busyness sample
period from 100 us to 10 ms to overccome (2).
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu
busyness state. Ensure that reset
is not in progress when the initial reset count is captured.
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git
On Tue, Oct 26, 2021 at 05:48:21PM -0700, Umesh Nerlige Ramappa wrote:
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide engine busyness to the user, GuC shares this info
with i915 for
ohn Harrison
Signed-off-by: Umesh Nerlige Ramappa
Acked-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 28 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 33 ++-
.../drm/i915/gt/intel_execlists_submission.c | 34 +++
drivers/gpu/drm/i915/gt/intel_gt_pm.c |
In preparation for GuC pmu stats, add a name to the execlists stats
structure so that it can be differentiated from the GuC stats.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 14 +++---
drivers/gpu/drm/i915/gt/intel_engine_stats.h | 33
On Tue, Oct 19, 2021 at 09:32:07AM +0100, Tvrtko Ursulin wrote:
On 18/10/2021 19:35, Umesh Nerlige Ramappa wrote:
On Mon, Oct 18, 2021 at 08:58:01AM +0100, Tvrtko Ursulin wrote:
On 16/10/2021 00:47, Umesh Nerlige Ramappa wrote:
With GuC handling scheduling, i915 is not aware of the time
On Mon, Oct 18, 2021 at 11:35:44AM -0700, Umesh Nerlige Ramappa wrote:
On Mon, Oct 18, 2021 at 08:58:01AM +0100, Tvrtko Ursulin wrote:
On 16/10/2021 00:47, Umesh Nerlige Ramappa wrote:
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the
On Mon, Oct 18, 2021 at 08:58:01AM +0100, Tvrtko Ursulin wrote:
On 16/10/2021 00:47, Umesh Nerlige Ramappa wrote:
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide engine busyness to
hin the busyness tolerances in selftest.
Signed-off-by: John Harrison
Signed-off-by: Umesh Nerlige Ramappa
Acked-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 28 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 33 ++-
.../drm/i915/gt/intel_execlists_submissio
In preparation for GuC pmu stats, add a name to the execlists stats
structure so that it can be differentiated from the GuC stats.
Signed-off-by: Umesh Nerlige Ramappa
Acked-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 14 +++---
drivers/gpu/drm/i915/gt
In preparation for GuC pmu stats, add a name to the execlists stats
structure so that it can be differentiated from the GuC stats.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 14 +++---
drivers/gpu/drm/i915/gt/intel_engine_stats.h | 33
ock takes care
of that.
Signed-off-by: John Harrison
Signed-off-by: Umesh Nerlige Ramappa
Acked-by: Tvrtko Ursulin
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 28 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 33 ++-
.../drm/i915/gt/intel_execlists_submission.c | 34 +++
driv
On Thu, Oct 14, 2021 at 09:21:28AM +0100, Tvrtko Ursulin wrote:
On 13/10/2021 01:56, Umesh Nerlige Ramappa wrote:
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide engine busyness to
On Wed, Oct 13, 2021 at 05:06:26PM +0100, Tvrtko Ursulin wrote:
On 13/10/2021 01:56, Umesh Nerlige Ramappa wrote:
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide engine busyness to
In preparation for GuC pmu stats, add a name to the execlists stats
structure so that it can be differentiated from the GuC stats.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 14 +++---
drivers/gpu/drm/i915/gt/intel_engine_stats.h | 33
esh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 28 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h | 33 ++-
.../drm/i915/gt/intel_execlists_submission.c | 34 +++
drivers/gpu/drm/i915/gt/intel_gt_pm.c | 2 +
drivers/gpu/drm/i915/gt/intel_reset.c |
On Mon, Oct 11, 2021 at 12:41:19PM +0100, Tvrtko Ursulin wrote:
On 07/10/2021 23:55, Umesh Nerlige Ramappa wrote:
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide engine busyness to
On Tue, Oct 05, 2021 at 04:14:23PM -0700, Matthew Brost wrote:
On Tue, Oct 05, 2021 at 10:47:11AM -0700, Umesh Nerlige Ramappa wrote:
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide
guc stats objects
- Since disable_submission is called from many places, move resetting
stats to intel_guc_submission_reset_prepare
Signed-off-by: John Harrison
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 28 +--
drivers/gpu/drm/i915
In preparation for GuC pmu stats, add a name to the execlists stats
structure so that it can be differentiated from the GuC stats.
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c| 14 +++---
drivers/gpu/drm/i915/gt/intel_engine_stats.h | 33
On Thu, Oct 07, 2021 at 09:17:34AM +0100, Tvrtko Ursulin wrote:
On 06/10/2021 21:45, Umesh Nerlige Ramappa wrote:
On Wed, Oct 06, 2021 at 10:11:58AM +0100, Tvrtko Ursulin wrote:
[snip]
@@ -762,12 +764,25 @@ submission_disabled(struct intel_guc *guc)
static void disable_submission(struct
On Wed, Oct 06, 2021 at 10:11:58AM +0100, Tvrtko Ursulin wrote:
On 05/10/2021 18:47, Umesh Nerlige Ramappa wrote:
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide engine busyness to
On Mon, Oct 04, 2021 at 04:21:44PM +0100, Tvrtko Ursulin wrote:
On 24/09/2021 23:34, Umesh Nerlige Ramappa wrote:
With GuC handling scheduling, i915 is not aware of the time that a
context is scheduled in and out of the engine. Since i915 pmu relies on
this info to provide engine busyness to
ath
- Drop inline
- Move spinlock and worker inits to guc initialization
- Drop helpers that are called only once
Signed-off-by: John Harrison
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 26 +-
drivers/gpu/drm/i915/gt/intel_engine_types.h |
fic details
Signed-off-by: John Harrison
Signed-off-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 26 +--
drivers/gpu/drm/i915/gt/intel_engine_types.h | 82 ---
.../drm/i915/gt/intel_execlists_submission.c | 32 +++
.../gpu/drm/i915/gt/uc/abi/guc_actions_ab
On Tue, Aug 31, 2021 at 02:55:37PM +0200, Daniel Vetter wrote:
On Mon, Aug 30, 2021 at 12:38:51PM -0700, Umesh Nerlige Ramappa wrote:
i915 used to support time based sampling mode which is good for overall
system monitoring, but is not enough for query mode used to measure a
single draw call or
0: Update uapi comment (Ashutosh)
Signed-off-by: Piotr Maciejewski
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_mman.h | 2 +
drivers/gpu/drm/i915/i915_perf.c
intel_uncore_rmw and REG_BIT (Chris)
Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL")
Signed-off-by: Piotr Maciejewski
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 9 +
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 fil
ly_whitelist.
- Grow the wal->list when adding whitelist registers after driver load.
v11:
- Fix memory leak in _wa_list_grow (Chris)
- Serialize kfree with engine resume using uncore->lock (Umesh)
- Grow the list only if wal->count is not aligned (Umesh)
Signed-off-by: Piotr Maciejew
Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 59
drivers/gpu/drm/i915/gt/intel_workarounds.h | 7 +
.../gpu/drm/i915/gt/selftest_workarounds.c| 267 ++
3 files changed, 333 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b
slots. Remove GPU_TICKS and A20 counter (Piotr)
- Whitelist registers only if perf_stream_paranoid is set to 0 (Jon)
v6: Move oa whitelist array to i915_perf (Chris)
Signed-off-by: Piotr Maciejewski
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915
From: Chris Wilson
Strip the encoded bits from the register offset so that we only use the
address for looking up the RING_NONPRIV entry.
Signed-off-by: Chris Wilson
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 66 +
1 file changed
From: Chris Wilson
Switch the search and grow code of the _wa_add to use _wa_index and
_wa_list_grow.
Signed-off-by: Chris Wilson
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 124 +++-
1 file changed, 71 insertions(+), 53 deletions
buffer quickly, the OA
buffer is mmapped into the user space.
This series implements the new query mechanism.
v2: Fix BAT failure (Umesh)
v3: Fix selftest (Umesh)
v4: Update uapi comment (Umesh)
Test-with: 20210830193337.15260-1-umesh.nerlige.rama...@intel.com
Signed-off-by: Umesh Nerlige Ramappa
: Umesh Nerlige Ramappa
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 46 ++---
1 file changed, 32 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 94e1937f8d29
On Tue, Aug 03, 2021 at 01:18:38PM -0700, Umesh Nerlige Ramappa wrote:
+ Joonas
On Tue, Aug 03, 2021 at 01:13:41PM -0700, Umesh Nerlige Ramappa wrote:
This is a revival of the patch series to support triggered perf query reports
from here - https://patchwork.freedesktop.org/series/83831/
The
+ Joonas
On Tue, Aug 03, 2021 at 01:13:41PM -0700, Umesh Nerlige Ramappa wrote:
This is a revival of the patch series to support triggered perf query reports
from here - https://patchwork.freedesktop.org/series/83831/
The patches were not pushed earlier because corresponding UMD changes were
intel_uncore_rmw and REG_BIT (Chris)
Fixes: 00a7f0d7155c ("drm/i915/tgl: Add perf support on TGL")
Signed-off-by: Piotr Maciejewski
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_perf.c | 9 +
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 fil
RING_NONPRIV.
Care must still be taken since the RING_NONPRIV are global, so any and
all contexts that run at the same time as the OA client, will also be
able to adjust the registers from their execbuf.
v2: Fix memmove size (Umesh)
Signed-off-by: Chris Wilson
Reviewed-by: Umesh Nerlige Ramappa
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu/drm/i915/gem/i915_gem_mman.h | 2 +
drivers/gpu/drm/i915/i915_perf.c | 126 ++-
include/uapi/drm/i915_drm.h | 33 ++
4
: Umesh Nerlige Ramappa
Reviewed-by: Chris Wilson
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 46 ++---
1 file changed, 32 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 053fa7251cd0
From: Chris Wilson
Switch the search and grow code of the _wa_add to use _wa_index and
_wa_list_grow.
Signed-off-by: Chris Wilson
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 124 +++-
1 file changed, 71 insertions(+), 53 deletions
slots. Remove GPU_TICKS and A20 counter (Piotr)
- Whitelist registers only if perf_stream_paranoid is set to 0 (Jon)
v6: Move oa whitelist array to i915_perf (Chris)
Signed-off-by: Piotr Maciejewski
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915
From: Chris Wilson
Strip the encoded bits from the register offset so that we only use the
address for looking up the RING_NONPRIV entry.
Signed-off-by: Chris Wilson
Reviewed-by: Umesh Nerlige Ramappa
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 66 +
1 file changed
buffer quickly, the OA
buffer is mmapped into the user space.
This series implements the new query mechanism.
Signed-off-by: Umesh Nerlige Ramappa
Chris Wilson (3):
drm/i915/gt: Refactor _wa_add to reuse wa_index and wa_list_grow
drm/i915/gt: Check for conflicting RING_NONPRIV
drm/i915/gt
ly_whitelist.
- Grow the wal->list when adding whitelist registers after driver load.
v11:
- Fix memory leak in _wa_list_grow (Chris)
- Serialize kfree with engine resume using uncore->lock (Umesh)
- Grow the list only if wal->count is not aligned (Umesh)
Signed-off-by: Piotr Maciejew
cs cycles to the uapi
Signed-off-by: Umesh Nerlige Ramappa
Test-with: 20210504001003.69445-1-umesh.nerlige.rama...@intel.com
Umesh Nerlige Ramappa (1):
i915/query: Correlate engine and cpu timestamps with better accuracy
drivers/gpu/drm/i915/i915_query.c | 157
GRAPHICS_VER instead.
v12: (Jason)
- Split cpu timestamp array into timestamp and delta for cleaner API
v13:
- Return the width of cs cycles
- Conform to kernel doc format
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
Reviewed-by: Jason Ekstrand
---
drivers/gpu/drm/i915
On Sat, May 01, 2021 at 10:27:03AM -0500, Jason Ekstrand wrote:
On April 30, 2021 23:01:44 "Dixit, Ashutosh"
wrote:
On Fri, 30 Apr 2021 19:19:59 -0700, Umesh Nerlige Ramappa wrote:
On Fri, Apr 30, 2021 at 07:35:41PM -0500, Jason Ekstrand wrote:
On April 30,
On Fri, Apr 30, 2021 at 07:35:41PM -0500, Jason Ekstrand wrote:
On April 30, 2021 18:00:58 "Dixit, Ashutosh"
wrote:
On Fri, 30 Apr 2021 15:26:09 -0700, Umesh Nerlige Ramappa wrote:
Looks like the engine can be dropped since all timestamps are in sync.
I
jus
On Thu, Apr 29, 2021 at 02:07:58PM -0500, Jason Ekstrand wrote:
On Wed, Apr 28, 2021 at 7:34 PM Umesh Nerlige Ramappa
wrote:
Perf measurements rely on CPU and engine timestamps to correlate
events of interest across these time domains. Current mechanisms get
these timestamps separately and
GRAPHICS_VER instead.
v12: (Jason)
- Split cpu timestamp array into timestamp and delta for cleaner API
Signed-off-by: Umesh Nerlige Ramappa
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/i915/i915_query.c | 148 ++
include/uapi/drm/i915_drm.h | 52
: Umesh Nerlige Ramappa
Test-with: 20210429002959.69473-1-umesh.nerlige.rama...@intel.com
Umesh Nerlige Ramappa (1):
i915/query: Correlate engine and cpu timestamps with better accuracy
drivers/gpu/drm/i915/i915_query.c | 148 ++
include/uapi/drm/i915_drm.h | 52
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