:
drm/exynos: do not start enabling DP at bind() phase
But for now driver need to read edid message in .get_modes()
function, so controller must be inited in bind time, so we
need to add controller init back.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Changes in v10: None
os: do not start enabling DP at bind() phase
But for now the connector status don't hardcode to connected,
need to operate dp phy in .detect function, so we need to revert
parts if Gustavo Padovan's changes, add phy poweron
function in bind time.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Ca
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang
Tested-by: Javier Martine
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Changes in v10:
- Remove the surplus "plat_data" check. (Heiko)
- switch (dp-
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes
From: Mark Yao <y...@rock-chips.com>
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao
Signed-off-by: Yakir Yang
---
Changes in v10: None
Changes in v9: None
Changes in v8
Add dt binding documentation for rockchip display port PHY.
Signed-off-by: Yakir Yang
Reviewed-by: Heiko Stuebner
---
Changes in v10: None
Changes in v9: None
Changes in v8:
- Remove the specific address in the example node name. (Heiko)
Changes in v7:
- Simplify the commit message. (Kishon
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Signed-off-by: Yakir Yang
Reviewed-by: Heiko Stuebner
---
Changes in v10:
- Fix the wrong macro value of GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK
BIT(4) -> BIT(20)
Chan
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang
Reviewed-by: Heiko Stuebner
---
Changes in v10: None
Changes in v9:
- Document more details for 'ports' property.
Changes in v8
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Changes in v10:
- Correct the ROCKCHIP_ANALOGIX_DP indentation in Kconfig
compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Signed-off-by: Yakir Yang
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
---
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
-by: Yakir Yang
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
---
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
compatibility of "hsync-active-high" "vs
, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang
Tested-by: Javier Martinez Canillas
---
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Signed-off-by: Yakir Yang
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
---
Changes in v10: None
Changes in v9: None
Changes in v8: None
init the connector.
They reason why connector need register in helper driver is rockchip drm
haven't implement the atomic API, but Exynos drm have implement it, so
there would need two different connector helper functions, that's why we
leave the connector register in helper driver.
Signed-off-by:
rd. Also I have
tested on Samsung Snow and Peach Pit Chromebooks, and thanks to Javier at
Samsung
help to retest the whole series on Samsung Exynos5800 Peach Pi Chromebook,
glad to say that things works rightlly.
Thanks,
- Yakir
Changes in v10:
- Correct the ROCKCHIP_ANALOGIX_DP indentation
Hi Heiko,
On 11/27/2015 09:32 PM, Heiko Stübner wrote:
> Am Mittwoch, 28. Oktober 2015, 16:56:01 schrieb Yakir Yang:
>> There are some IP limit on rk3288 that only support 4 physical lanes
>> of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
>>
>> Tested-b
send the whole
series out that update the version to v10.
Thanks
- Yakir
On 11/27/2015 01:30 AM, Heiko Stübner wrote:
> Hi Yakir,
>
> Am Mittwoch, 28. Oktober 2015, 16:21:59 schrieb Yakir Yang:
>> Split the dp core driver from exynos directory to bridge directory,
>> and r
Hi Heiko,
On 11/22/2015 04:14 AM, Heiko Stuebner wrote:
> Hi Yakir,
>
> Am Mittwoch, 11. November 2015, 15:47:32 schrieb Yakir Yang:
>> Signed-off-by: Yakir Yang
>> ---
>> .../display/rockchip/inno_hdmi-rockchip.txt| 50
>> ++
&
des driver export an interface for specific platform
driver that used for passing the encrypted HDCP key.
Signed-off-by: Yakir Yang
---
drivers/gpu/drm/bridge/dw_hdmi.c | 355 ---
drivers/gpu/drm/bridge/dw_hdmi.h | 20 +++
include/drm/bridge/dw_hdmi.h
has enabled protection, it will update the the value with the KSV
(or similarly unique identifier, if not using HDCP) of the first-hop
device (sink or repeater).
Signed-off-by: Sean Paul
Signed-off-by: Yakir Yang
---
drivers/gpu/drm/drm_crtc.c | 21 +
drivers/gpu/drm/drm_sysfs
ork.kernel.org/patch/7279801
[Rebased on] Vladimir Zapolskiy: https://patchwork.kernel.org/patch/7279801
Thanks
- Yakir
Sean Paul (1):
drm: Add Content Protection properties to drm
Yakir Yang (1):
drm: bridgw/dw_hdmi: add basic hdmi hdcp driver
drivers/gpu/drm/br
hout new changes but rebased on the latest kernel again and
again. If you thought those patches is fine, it would be very grateful to
give some ACKs to those changes.
Thanks,
- Yakir
On 10/28/2015 04:15 PM, Yakir Yang wrote:
> Hi all,
>
> The Samsung Exynos eDP controller and Rockchip RK32
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
---
Changes in v10:
- Fix the wrong macro value of GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK (Brian)
BIT(4) -> BIT
Hi Brian,
Thank you for debugging, and fell sorry for the delay reply
On 11/06/2015 07:45 AM, Brian Norris wrote:
> Hi,
>
> A few updates:
>
> On Tue, Nov 03, 2015 at 05:13:48PM -0800, Brian Norris wrote:
>> On Wed, Nov 04, 2015 at 08:48:38AM +0800, Yakir Yang wrote:
>&
On 11/13/2015 07:38 AM, Rob Herring wrote:
> On Thu, Nov 12, 2015 at 09:27:21AM +0800, Yakir Yang wrote:
>> Hi Rob,
>>
>> On 11/12/2015 07:10 AM, Rob Herring wrote:
>>> On Fri, Oct 30, 2015 at 09:09:15AM +0800, Yakir Yang wrote:
>>>> Some edp screen do no
Hi Heiko,
On 11/12/2015 07:23 AM, Heiko Stuebner wrote:
> Hi Yakir,
>
> Am Mittwoch, 28. Oktober 2015, 16:30:33 schrieb Yakir Yang:
>> Add phy driver for the Rockchip DisplayPort PHY module. This
>> is required to get DisplayPort working in Rockchip SoCs.
>>
>
Hi Rob,
On 11/12/2015 07:10 AM, Rob Herring wrote:
> On Fri, Oct 30, 2015 at 09:09:15AM +0800, Yakir Yang wrote:
>> Some edp screen do not have hpd signal, so we can't just return
>> failed when hpd plug in detect failed.
>>
>> This is an hardware property, so we nee
Hi Rob,
On 11/12/2015 04:22 AM, Rob Herring wrote:
> On Wed, Nov 11, 2015 at 03:47:32PM +0800, Yakir Yang wrote:
>> Signed-off-by: Yakir Yang
> Acked-by: Rob Herring
Thanks you for responding ;)
- Yakir
>> ---
>> .../display/rockchip/inno_hdmi-
Signed-off-by: Yakir Yang
---
.../display/rockchip/inno_hdmi-rockchip.txt| 50 ++
1 file changed, 50 insertions(+)
create mode 100644
Documentation/devicetree/bindings/display/rockchip/inno_hdmi-rockchip.txt
diff --git
a/Documentation/devicetree/bindings/display
The Innosilicon HDMI is a low power HDMI 1.4 transmitter
IP, and it have been integrated on some rockchip CPUs
(like RK3036, RK312x).
Signed-off-by: Yakir Yang
---
drivers/gpu/drm/rockchip/Kconfig |8 +
drivers/gpu/drm/rockchip/Makefile|1 +
drivers/gpu/drm/rockchip/inno_hdmi.c
CPUs haven't been landed on manline kernel, so I creat a branch to
verify this series [https://github.com/rockchip-linux/kernel].
- Yakir
Yakir Yang (2):
drm: rockchip/hdmi: add Innosilicon HDMI support
dt-bindings: add document for Innosilicon HDMI on Rockchip platform
.../display
blem on RK3036 SDK board, and this
could fix my problem, so
Tested-by: Yakir Yang
- Yakir
> ---
> drivers/gpu/drm/rockchip/rockchip_drm_vop.c |4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
> b/drivers
Hi Brain,
On 11/03/2015 12:38 PM, Brian Norris wrote:
> Hi Yakir,
>
> On Thu, Oct 29, 2015 at 09:58:38AM +0800, Yakir Yang wrote:
>> Add phy driver for the Rockchip DisplayPort PHY module. This
>> is required to get DisplayPort working in Rockchip SoCs.
>>
>> Revi
On 11/01/2015 02:37 AM, Rob Herring wrote:
> On Sat, Oct 31, 2015 at 1:42 AM, Yakir Yang wrote:
>> Rockchip DP driver is a helper driver of analogix_dp coder driver,
>> so most of the DT property should be descriped in analogix_dp document.
>>
>> Reviewed-by: He
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
---
Changes in v10:
- Removed the duplicated signed-of.
Changes in v9:
- Document more details
On 10/31/2015 02:30 PM, Yakir Yang wrote:
> Rockchip DP driver is a helper driver of analogix_dp coder driver,
> so most of the DT property should be descriped in analogix_dp document.
>
> Signed-off-by: Yakir Yang
>
> Signed-off-by: Yakir Yang
> Reviewed-by: Heiko S
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang
Signed-off-by: Yakir Yang
Reviewed-by: Heiko Stuebner
---
Changes in v9:
- Document more details for 'ports' property.
Changes
Hi Rob,
On 10/31/2015 12:46 AM, Rob Herring wrote:
> On Wed, Oct 28, 2015 at 3:28 AM, Yakir Yang wrote:
>> Rockchip DP driver is a helper driver of analogix_dp coder driver,
>> so most of the DT property should be descriped in analogix_dp document.
>>
>> Reviewed-by
On 10/31/2015 12:42 AM, Rob Herring wrote:
> On Wed, Oct 28, 2015 at 3:31 AM, Yakir Yang wrote:
>> Add dt binding documentation for rockchip display port PHY.
>>
>> Reviewed-by: Heiko Stuebner
>> Signed-off-by: Yakir Yang
> Acked-by: Rob Herring
Thanks,
-
as
Signed-off-by: Yakir Yang
---
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Add "analogix,need-force-hpd" to indicate whether driver need foce
hpd when hpd detect failed.
Changes in v2: None
Hi Heiko,
On 10/30/2015 01:49 AM, Heiko Stuebner wrote:
> Am Mittwoch, 28. Oktober 2015, 16:15:43 schrieb Yakir Yang:
>> Hi all,
>>
>> The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
>> share the same IP, so a lot of parts can be re-used.
On 10/29/2015 04:40 PM, Heiko Stuebner wrote:
> Am Donnerstag, 29. Oktober 2015, 09:12:21 schrieb Yakir Yang:
>> Hi Heiko,
>>
>> On 10/29/2015 04:02 AM, Heiko Stuebner wrote:
>>> Hi Yakir,
>>>
>>> Am Mittwoch, 28. Oktober 2015, 16:26:33 schrieb Y
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
---
Changes in v9:
- Removed the unused the variable "res" in probe function. (Heiko)
- Removed the unused
Hi Heiko,
On 10/29/2015 04:36 AM, Heiko Stuebner wrote:
> Hi Yakir,
>
> Am Mittwoch, 28. Oktober 2015, 16:30:33 schrieb Yakir Yang:
>> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
>> +{
>> +struct device *dev = >dev;
>> +s
Hi Heiko,
On 10/29/2015 04:02 AM, Heiko Stuebner wrote:
> Hi Yakir,
>
> Am Mittwoch, 28. Oktober 2015, 16:26:33 schrieb Yakir Yang:
>> diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
>> b/Documentation/devicetree/bindings/display/exynos/exynos_dp
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
C
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes
From: Mark Yao <y...@rock-chips.com>
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6
Add dt binding documentation for rockchip display port PHY.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
---
Changes in v8:
- Remove the specific address in the example node name. (Heiko)
Changes in v7:
- Simplify the commit message. (Kishon)
Changes in v6: None
Changes in v5
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
---
Changes in v8:
- Fix the mixed spacers on macro definitions. (Heiko)
- Remove the unnecessary empty line after
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Reviewed-by: Heiko Stuebner
Signed-off-by: Yakir Yang
---
Changes in v8:
- Modify the commit subject name. (Heiko)
Changes in v7: None
Changes in v6: None
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5
compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6:
- Fix Peach Pit hpd property name
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
to avo
, 2.7Gbps, 5.4Gbps}.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
Changes in v3:
- The link_rate
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
driver is rockchip drm
haven't implement the atomic API, but Exynos drm have implement it, so
there would need two different connector helper functions, that's why we
leave the connector register in helper driver.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v8: None
rd. Also I have
tested on Samsung Snow and Peach Pit Chromebooks, and thanks to Javier at
Samsung
help to retest the whole series on Samsung Exynos5800 Peach Pi Chromebook,
glad to say that things works rightlly.
Thanks,
- Yakir
Changes in v8:
- Correct the right document path of display-timing.
On 10/28/2015 07:08 AM, Heiko Stuebner wrote:
> Am Samstag, 24. Oktober 2015, 11:06:37 schrieb Yakir Yang:
>> Add dt binding documentation for rockchip display port PHY.
>>
>> Tested-by: Javier Martinez Canillas
>> Signed-off-by: Yakir Yang
>> ---
>> Cha
On 10/28/2015 05:24 AM, Heiko Stuebner wrote:
> Am Samstag, 24. Oktober 2015, 11:06:37 schrieb Yakir Yang:
>> Add dt binding documentation for rockchip display port PHY.
>>
>> Tested-by: Javier Martinez Canillas
>> Signed-off-by: Yakir Yang
>> ---
> phy bi
ktober 2015, 11:06:03 schrieb Yakir Yang:
>> Rockchip DP driver is a helper driver of analogix_dp coder driver,
>> so most of the DT property should be descriped in analogix_dp document.
>>
>> Tested-by: Javier Martinez Canillas
>> Signed-off-by: Yakir Yang
> everything
Hi Heiko,
On 10/28/2015 05:04 AM, Heiko Stuebner wrote:
> Hi Yakir,
>
> Am Samstag, 24. Oktober 2015, 11:06:00 schrieb Yakir Yang:
>> Analogix dp driver is split from exynos dp driver, so we just
>> make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
>>
&
On 10/28/2015 05:23 AM, Heiko Stuebner wrote:
> Am Samstag, 24. Oktober 2015, 11:06:04 schrieb Yakir Yang:
>> Add phy driver for the Rockchip DisplayPort PHY module. This
>> is required to get DisplayPort working in Rockchip SoCs.
>>
>> Tested-by: Javier Martinez Canill
On 10/28/2015 05:23 AM, Heiko Stuebner wrote:
> Am Samstag, 24. Oktober 2015, 11:06:04 schrieb Yakir Yang:
>> Add phy driver for the Rockchip DisplayPort PHY module. This
>> is required to get DisplayPort working in Rockchip SoCs.
>>
>> Tested-by: Javier Martinez Canill
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6: None
Changes
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
C
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Tested-by: Javier Martinez Canillas
Signed-off-by:
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Seprate the link
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable
From: Mark Yao <y...@rock-chips.com>
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6: None
Changes in v5:
Add dt binding documentation for rockchip display port PHY.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Update the rockchip,grf explain in document, and correct
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6:
- Simply the commit message. (Kishon)
- Symmetrical enable/disbale the phy
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6: None
Changes in v5:
- Split binding doc's from driver
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6: None
Changes in v5:
- Remove the empty
compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6:
- Fix Peach Pit hpd property name error:
- hpd
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
to avoid -EOVERFLOW er
, 2.7Gbps, 5.4Gbps}.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
Changes in v3:
- The link_rate and lane_count shouldn't
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Reviewed-by: Krzysztof Kozlowski
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
Changes in v6: None
Changes in v5
driver is rockchip drm
haven't implement the atomic API, but Exynos drm have implement it, so
there would need two different connector helper functions, that's why we
leave the connector register in helper driver.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
Ch
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
---
Changes in v7: None
rzysztof's reviewed and Javier's test and some comment Kishon during this
time), is there any chances to share some ackes from Exynos DRM maintainers
and Bridge maintainers?
Best regards,
- Yakir
Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
compatibility
Hi Javier,
On 10/20/2015 05:48 PM, Javier Martinez Canillas wrote:
> Hello Yakir,
>
> On 10/20/2015 04:10 AM, Yakir Yang wrote:
>> Hi Javier,
>>
>> On 10/19/2015 06:40 PM, Javier Martinez Canillas wrote:
>>> Hello Yakir,
>>>
>>>
Hi Javier,
On 10/19/2015 06:40 PM, Javier Martinez Canillas wrote:
> Hello Yakir,
>
> On 10/10/2015 05:35 PM, Yakir Yang wrote:
>> Hi all,
>>
>> The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
>> share the same IP, so a lot of parts c
Hi Javierm
On 10/13/2015 05:21 PM, Javier Martinez Canillas wrote:
> Hello Yakir,
>
> Sorry for the delay but I was on holidays.
>
> On 10/10/2015 04:31 PM, Yakir Yang wrote:
>> Hi Javier,
> [snip]
>
>>>>> Maybe you can email me the method the run ma
Hi Kishon,
On 10/13/2015 06:28 AM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Saturday 10 October 2015 09:28 PM, Yakir Yang wrote:
>> This phy driver is binded with the Rockchip DisplayPort
>> driver, here are the brief properties:
>> edp_phy: edp-phy at ff770274 {
Hi Kishon
On 10/12/2015 11:02 PM, Kishon Vijay Abraham I wrote:
> Hi,
>
> On Saturday 10 October 2015 09:25 PM, Yakir Yang wrote:
>> This phy driver would control the Rockchip DisplayPort module
>> phy clock and phy power, it is relate to analogix_dp-rockchip
>> dp d
On 10/12/2015 02:54 PM, Krzysztof Kozlowski wrote:
> On 12.10.2015 13:29, Yakir Yang wrote:
>> Both hsync/vsync polarity and interlace mode can be parsed from
>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>> by the video code.
>>
>> B
-by: Yakir Yang
---
*just add a note that this is v7 of only fifth patch.*
Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
to avoid -EOVERFLOW error (Krzysztof
On 10/12/2015 11:51 AM, Krzysztof Kozlowski wrote:
> On 12.10.2015 11:43, Yakir Yang wrote:
>> On 10/12/2015 08:49 AM, Krzysztof Kozlowski wrote:
>>> On 12.10.2015 09:37, Yakir Yang wrote:
>>>> Hi Krzysztof,
>>>>
>>>> On 10/10/2015 11:46
On 10/12/2015 08:49 AM, Krzysztof Kozlowski wrote:
> On 12.10.2015 09:37, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> On 10/10/2015 11:46 PM, Yakir Yang wrote:
>>> Both hsync/vsync polarity and interlace mode can be parsed from
>>> drm display mode, and dyn
Hi Krzysztof,
On 10/10/2015 11:46 PM, Yakir Yang wrote:
> Both hsync/vsync polarity and interlace mode can be parsed from
> drm display mode, and dynamic_range and ycbcr_coeff can be judge
> by the video code.
>
> But presumably Exynos still relies on the DT properties, so
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Call drm_panel_prepare
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Take Jingoo suggest, add commit me
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