Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Call drm_panel_prepare() in
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Take Jingoo suggest, add commit me
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Chan
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Seprate the link-rate and lane-count limit out with the device_type
flag
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error
From: Mark Yao
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Fix compiled error (Heiko)
- Using the
24M>;
clock-names = "24m";
#phy-cells = <0>;
};
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Update the rockchip,grf explain in document, and correct the clock requir
This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip platform,
then you should select both of them.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Remove
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Remove the empty line at the end of document, and correct the endpoint
compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Yakir Yang
---
Changes in v6:
- Fix Peach Pit hpd property name error:
- hpd-gpio = <&gpx2 6 0>;
+ hpd-gpios =
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5
: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
to get the backword timing values. Krzysztof suggest me that driver could use
the "of_property_read_bool" to get backword timing valu
2Gbps, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
Changes in v3:
- The link_rate and lane_count shouldn't config to the DT property value
directly, but w
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Yakir Yang
---
Changes in v6: None
Changes in v5:
- Resequence this patch after analogix_dp driver have been split
er is rockchip drm
haven't implement the atomic API, but Exynos drm have implement it, so
there would need two different connector helper functions, that's why we
leave the connector register in helper driver.
Signed-off-by: Yakir Yang
---
Changes in v6:
- Fix the Kconfig recursive depen
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang
---
Changes in v6:
- Fix the wrong code in previous series
choice not to debug
more depth.
That's to say if someone want to test this series, I suggest you applied this
series on tag-20150918, just need to fix some light conflicts with the 01 & 02
patches (or just email me, I can send you directly).
Thanks,
- Yakir
Changes in v6:
- Fix the wrong
Hi Javier,
On 10/08/2015 08:40 AM, Yakir Yang wrote:
> On 10/07/2015 07:25 PM, Javier Martinez Canillas wrote:
>> On 10/07/2015 01:05 PM, Yakir Yang wrote:
>>> On 10/07/2015 05:26 PM, Javier Martinez Canillas wrote:
>>>> On 10/07/2015 11:02 AM, Yakir Yang wrote
Oh, I haven't noticed that those patches already have been
merged into linux-next :-)
On 10/08/2015 03:17 AM, Russell King - ARM Linux wrote:
> On Wed, Oct 07, 2015 at 06:40:11PM +0800, Yakir Yang wrote:
>>
>> On 10/07/2015 05:48 PM, Russell King - ARM Linux wrote:
>>
Hi Javier,
On 10/07/2015 07:25 PM, Javier Martinez Canillas wrote:
> Hello Yakir,
>
> On 10/07/2015 01:05 PM, Yakir Yang wrote:
>> Hi Javier,
>>
>> On 10/07/2015 05:26 PM, Javier Martinez Canillas wrote:
>>> Hello Yakir,
>>>
>>> On
Hi Javier,
On 10/07/2015 05:26 PM, Javier Martinez Canillas wrote:
> Hello Yakir,
>
> On 10/07/2015 11:02 AM, Yakir Yang wrote:
>> Hi Javier,
>>
>> On 10/07/2015 04:46 PM, Javier Martinez Canillas wrote:
>>> Hello Yakir,
>>>
>>>
On 10/07/2015 05:48 PM, Russell King - ARM Linux wrote:
> On Wed, Oct 07, 2015 at 12:05:37PM +0800, Yakir Yang wrote:
>>
>> On 08/09/2015 12:04 AM, Russell King wrote:
>>> The dw_hdmi enable/disable handling is particularly weak in several
>>> regards:
>&
On 10/07/2015 05:18 PM, Russell King - ARM Linux wrote:
> On Wed, Oct 07, 2015 at 11:50:53AM +0800, Yakir Yang wrote:
>>
>> On 08/09/2015 12:04 AM, Russell King wrote:
>>> On a mode set, DRM makes the following sequence of calls:
>>> * for_each_encoder
>>&
Hi Javier,
On 10/07/2015 04:46 PM, Javier Martinez Canillas wrote:
> Hello Yakir,
>
> On 10/07/2015 08:25 AM, Yakir Yang wrote:
>> Hi all,
>>
>> Friendly ping. :)
>>
>>
>> Best regards,
>> - Yakir
>>
>>
> Do you have a tree t
Hi all,
Friendly ping. :)
Best regards,
- Yakir
On 09/22/2015 03:20 PM, Yakir Yang wrote:
> Hi all,
>
> The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
> share the same IP, so a lot of parts can be re-used. I split the common
> code into bridge
uot;);
>
> - hdmi_modb(hdmi, HDMI_PHY_HPD, HDMI_PHY_HPD,
> - HDMI_PHY_POL0);
> -
> - dw_hdmi_poweroff(hdmi);
> + if (!hdmi->disabled)
> + dw_hdmi_powerof
dmi document, great clean, wish I have the
qualification to share review. (If no, that's fine :) )
Reviewed-by: Yakir Yang
- Yakir
> This can be seen as the bit has no effect when the HDMI phy is
> operational on iMX6 hardware.
>
> Rename the function to dw_hdmi_phy_enable_powerd
dw_hdmi_poweroff(hdmi);// no need here
}
drm_helper_hpd_irq_event(hdmi->connector.dev);
}
..
}
Thanks,
- Yakir
> ---
> drivers/gpu/drm/bridge/dw_hdmi.c | 2 --
> 1 file changed, 2 deletions(-)
>
> diff --git
Some to 06/12 reply.
Tested-by: Yakir Yang
- Yakir
> ---
> drivers/gpu/drm/bridge/dw_hdmi.c | 12 +---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/dw_hdmi.c
> b/drivers/gpu/drm/bridge/dw_hdmi.c
> index 7f764716f3c4.
before, feel better about
this one, and I have backport those 06/12 & 07/12 to chrome-3.14
tree, audio still works rightly when I changing the display resolutions.
So I would like to share:
Tested-by: Yakir Yang
Besides, Andy, would you like to share your ACK here :)
Best regards,
- Ya
Hi Krzysztof,
On 09/30/2015 04:26 PM, Krzysztof Kozlowski wrote:
> On 30.09.2015 17:20, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> On 09/30/2015 03:34 PM, Krzysztof Kozlowski wrote:
>>> On 30.09.2015 16:19, Yakir Yang wrote:
>>>> Hi Krzysztof,
>>>
Hi Krzysztof,
On 09/30/2015 03:34 PM, Krzysztof Kozlowski wrote:
> On 30.09.2015 16:19, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> On 09/30/2015 01:32 PM, Krzysztof Kozlowski wrote:
>>> On 22.09.2015 16:37, Yakir Yang wrote:
>>>> Both hsync/vsync pola
Hi Krzysztof,
On 09/30/2015 01:39 PM, Krzysztof Kozlowski wrote:
> On 22.09.2015 16:43, Yakir Yang wrote:
>> After exynos_dp have been split the common IP code into analogix_dp driver,
>> the analogix_dp driver have deprecated some Samsung platform properties which
>> could
Hi Krzysztof,
On 09/30/2015 01:32 PM, Krzysztof Kozlowski wrote:
> On 22.09.2015 16:37, Yakir Yang wrote:
>> Both hsync/vsync polarity and interlace mode can be parsed from
>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>> by the video code.
>>
>
Hi Krzysztof,
On 09/30/2015 01:22 PM, Krzysztof Kozlowski wrote:
> On 22.09.2015 16:34, Yakir Yang wrote:
>> Fix some obvious alignment problems, like alignment and line
>> over 80 characters problems, make this easy to be maintained
>> later.
>>
>> Signed-off-by:
Hi Krzysztof,
On 09/30/2015 01:17 PM, Krzysztof Kozlowski wrote:
> On 22.09.2015 16:29, Yakir Yang wrote:
>> Split the dp core driver from exynos directory to bridge directory,
>> and rename the core driver to analogix_dp_*, rename the platform
>> code to exynos_dp.
On 09/29/2015 05:55 PM, Yakir Yang wrote:
>
>
> On 09/29/2015 05:28 PM, Sjoerd Simons wrote:
>> When doing the initial setup both the hclk and the aclk need to be
>> enabled otherwise the board will simply hang. This only occurs when
>> building the vop driver as a mo
re the clock framework shuts of unused clocks
> (including the aclk).
>
> While there also switch to doing prepare and enable in one step rather
> then separate steps to reduce the amount of code required.
>
> Signed-off-by: Sjoerd Simons
Looks good and test on chromeos-3.14 tree, no
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4:
- Call drm_panel_prepare() in .get_modes function
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4:
- Take Jingoo suggest, add commit messages.
Changes in v3:
- m
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Chan
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4:
- Seprate the link-rate and lane-count limit out with the device_type
flag. (Thierry)
Changes in
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error
drivers/gpu/drm/bridge
From: Mark Yao
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao
Signed-off-by: Yakir Yang
---
Changes in v5:
- Fix compiled error (Heiko)
- Using the connector display info
24M>;
clock-names = "24m";
#phy-cells = <0>;
};
Signed-off-by: Yakir Yang
---
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Update the rockchip,grf explain in document, and correct the clock required
elemets in docu
This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip platform,
then you should select both of them.
Signed-off-by: Yakir Yang
---
Changes in v5:
- Remove "reg" D
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang
---
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko)
Changes
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang
---
Changes in v5:
- Remove the empty line at the end of document, and correct the endpoint
numbers in the example
compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Signed-off-by: Yakir Yang
---
Changes in v5:
- Correct the misspell in commit message. (Krzysztof)
Changes in v4:
- Separate all DTS changes to a separate patch. (Krzysztof)
Changes in v3
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4
: Yakir Yang
---
Changes in v5:
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
to get the backword timing values. Krzysztof suggest me that driver could use
the "of_property_read_bool" to get backword timing values, but that interfa
2Gbps, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
Changes in v3:
- The link_rate and lane_count shouldn't config to the DT property value
directly, but we can take those a
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Signed-off-by: Yakir Yang
---
Changes in v5:
- Resequence this patch after analogix_dp driver have been split
from exynos_dp code, and rephrase reasonable commit
er is rockchip drm
haven't implement the atomic API, but Exynos drm have implement it, so
there would need two different connector helper functions, that's why we
leave the connector register in helper driver.
Signed-off-by: Yakir Yang
---
Changes in v5:
- Correct the check condition
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang
---
Changes in v5: None
Changes in v4: None
Changes in v3
el and chromeos-3.14 tree. ;)
Due to no Exynos board in my side, so I haven't verified the eDP function on
samsung platform, I only ensure that there are no obvious compiled error. Any
help would be greatly appreciated. :)
Thanks,
- Yakir
Changes in v5:
- Correct the check condition of gpio_i
Hi Thierry,
On 09/21/2015 07:22 PM, Thierry Reding wrote:
> On Mon, Sep 21, 2015 at 06:27:40PM +0800, Yakir Yang wrote:
>> Hi Thierry,
>>
>> Thanks for your suggest :)
>>
>> On 09/21/2015 05:15 PM, Thierry Reding wrote:
>>> On Mon, Sep 21, 2015 at 04:45:4
Hi Thierry,
Thanks for your suggest :)
On 09/21/2015 05:15 PM, Thierry Reding wrote:
> On Mon, Sep 21, 2015 at 04:45:44PM +0800, Yakir Yang wrote:
>> Hi Heiko,
>>
>> On 09/02/2015 10:15 AM, Yakir Yang wrote:
>>> Hi Heiko,
>>>
>>> å¨ 09/02/201
Hi Thierry & Rob,
Sorry, apologize for the delay in replying :-)
On 09/07/2015 04:20 PM, Thierry Reding wrote:
> On Sun, Sep 06, 2015 at 11:59:08AM +0800, Yakir Yang wrote:
>> Hi Thierry,
>>
>> å¨ 09/03/2015 05:04 PM, Thierry Reding åé:
>>> On Thu, Sep 0
Hi Heiko,
On 09/02/2015 10:15 AM, Yakir Yang wrote:
> Hi Heiko,
>
> å¨ 09/02/2015 05:47 AM, Heiko Stuebner åé:
>> Hi Yakir,
>>
>> Am Dienstag, 1. September 2015, 13:46:11 schrieb Yakir Yang:
>>> The Samsung Exynos eDP controller and Rockchip RK3288 eD
Hi Krzysztof,
å¨ 09/07/2015 08:22 AM, Krzysztof Kozlowski åé:
> On 06.09.2015 16:49, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> å¨ 09/04/2015 08:41 AM, Krzysztof Kozlowski åé:
>>> On 03.09.2015 14:30, Yakir Yang wrote:
>>>> Hi Krzysztof,
&g
Hi Krzysztof,
å¨ 09/07/2015 07:55 AM, Krzysztof Kozlowski åé:
> On 06.09.2015 13:07, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> å¨ 09/04/2015 08:36 AM, Krzysztof Kozlowski åé:
>>> On 01.09.2015 15:07, Yakir Yang wrote:
>>>
>>> Empty commit
Hi Rob,
å¨ 09/05/2015 05:46 AM, Rob Herring åé:
> On Wed, Sep 2, 2015 at 11:27 PM, Yakir Yang wrote:
>> Hi Rob,
>>
>> å¨ 09/03/2015 04:17 AM, Rob Herring åé:
>>> On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang wrote:
>>>> Some edp screen do no
Hi Krzysztof,
å¨ 09/04/2015 08:41 AM, Krzysztof Kozlowski åé:
> On 03.09.2015 14:30, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> å¨ 09/03/2015 08:58 AM, Krzysztof Kozlowski åé:
>>> On 01.09.2015 14:49, Yakir Yang wrote:
>>>> Split the dp c
Hi Heiko,
å¨ 09/03/2015 09:52 PM, Heiko Stuebner åé:
> Am Donnerstag, 3. September 2015, 11:25:00 schrieb Yakir Yang:
>> å¨ 09/02/2015 09:27 PM, Rob Herring åé:
>>> On Tue, Sep 1, 2015 at 1:04 AM, Yakir Yang wrote:
>>>> +- clocks: from common clo
Hi Krzysztof,
å¨ 09/04/2015 08:36 AM, Krzysztof Kozlowski åé:
> On 01.09.2015 15:07, Yakir Yang wrote:
>
> Empty commit message. Please explain here why you want to add platform
> device type support.
>
> Actually the title is confusing. You are not adding support for platf
Hi Thierry,
å¨ 09/03/2015 05:04 PM, Thierry Reding åé:
> On Thu, Sep 03, 2015 at 12:27:47PM +0800, Yakir Yang wrote:
>> Hi Rob,
>>
>> å¨ 09/03/2015 04:17 AM, Rob Herring åé:
>>> On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang wrote:
>>>> Some edp
Hi Thierry,
å¨ 09/03/2015 04:38 PM, Thierry Reding åé:
> On Wed, Sep 02, 2015 at 06:02:25PM +0800, Yakir Yang wrote:
>> å¨ 2015/9/2 16:34, Thierry Reding åé:
> [...]
>>> At the very least your code must compile when applied against a recent
>>> upstream tr
Hi Krzysztof,
å¨ 09/03/2015 04:04 PM, Krzysztof Kozlowski åé:
> On 01.09.2015 14:55, Yakir Yang wrote:
>> Both hsync/vsync polarity and interlace mode can be parsed from
>> drm display mode, and dynamic_range and ycbcr_coeff can be judge
>> by the video code, same to
Hi Joe,
å¨ 09/03/2015 01:57 PM, Joe Perches åé:
> On Thu, 2015-09-03 at 13:33 +0800, Yakir Yang wrote:
> []
>>>>>> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c
> []
>>>>>> @@ -155,24 +156,22 @@ static int exynos_dp
Hi Krzysztof,
å¨ 09/03/2015 01:08 PM, Krzysztof Kozlowski åé:
> On 03.09.2015 14:04, Yakir Yang wrote:
>> Hi Krzysztof,
>>
>> å¨ 09/03/2015 08:21 AM, Krzysztof Kozlowski åé:
>>> On 01.09.2015 14:46, Yakir Yang wrote:
>>>> After run "chec
Hi Krzysztof,
å¨ 09/03/2015 08:58 AM, Krzysztof Kozlowski åé:
> On 01.09.2015 14:49, Yakir Yang wrote:
>> Split the dp core driver from exynos directory to bridge
>> directory, and rename the core driver to analogix_dp_*,
>> leave the platform code to analogix_dp-exynos
Hi Krzysztof,
å¨ 09/03/2015 08:21 AM, Krzysztof Kozlowski åé:
> On 01.09.2015 14:46, Yakir Yang wrote:
>> After run "checkpatch.pl -f --subjective" command, I see there
>> are lots of alignment problem in exynos_dp driver, so let just
>> fix them.
> Hi,
>
Hi Krzysztof,
å¨ 09/03/2015 08:01 AM, Krzysztof Kozlowski åé:
> On 01.09.2015 15:01, Yakir Yang wrote:
>> After exynos_dp have been splited the common IP code into analogix_dp driver,
> s/splited/split/
Done :)
>> the analogix_dp driver have deprecated some samsung p
Hi Rob,
å¨ 09/03/2015 04:17 AM, Rob Herring åé:
> On Tue, Sep 1, 2015 at 1:14 AM, Yakir Yang wrote:
>> Some edp screen do not have hpd signal, so we can't just return
>> failed when hpd plug in detect failed.
> This is a property of the panel (or connector perha
Hi Emil,
å¨ 09/02/2015 10:50 PM, Emil Velikov åé:
> [Dropping the CC list]
Hmm...Don't understand what this means. If you can explain, that
would be better, so I would not miss your suggest. :-)
> Hi Yakir Yang,
>
> On 1 September 2015 at 06:49, Yakir Yang wrote:
>
Hi Rob,
å¨ 09/02/2015 09:27 PM, Rob Herring åé:
> On Tue, Sep 1, 2015 at 1:04 AM, Yakir Yang wrote:
>> This phy driver would control the Rockchip DisplayPort module
>> phy clock and phy power, it is relate to analogix_dp-rockchip
>> dp driver. If you want DP work
Thierry,
å¨ 2015/9/2 16:34, Thierry Reding åé:
> On Wed, Sep 02, 2015 at 10:06:36AM +0800, Yakir Yang wrote:
>> å¨ 09/02/2015 05:00 AM, Heiko Stuebner åé:
>>> Am Dienstag, 1. September 2015, 14:01:48 schrieb Yakir Yang:
> [...]
>>>> diff
Hi Heiko,
å¨ 09/02/2015 05:47 AM, Heiko Stuebner åé:
> Hi Yakir,
>
> Am Dienstag, 1. September 2015, 13:46:11 schrieb Yakir Yang:
>> The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
>> share the same IP, so a lot of parts can be re-used. I spl
Hi Heiko,
å¨ 09/02/2015 05:00 AM, Heiko Stuebner åé:
> Hi Yakir,
>
> Am Dienstag, 1. September 2015, 14:01:48 schrieb Yakir Yang:
>> From: Mark Yao
>>
>> Add bpc and color mode setting in rockchip_drm_vop driver, so
>> connector could try to use the edid
Hi Heiko,
å¨ 09/02/2015 05:00 AM, Heiko Stuebner åé:
> Hi Yakir,
>
> Am Dienstag, 1. September 2015, 14:01:28 schrieb Yakir Yang:
>> Rockchip have three clocks for dp controller, we leave pclk_edp
>> to analogix_dp driver control, and keep the sclk_edp_24m and
>>
Hi Heiko,
å¨ 09/02/2015 04:58 AM, Heiko Stuebner åé:
> Hi Yakir,
>
> small nit more below
>
> Am Dienstag, 1. September 2015, 18:51:16 schrieb Heiko Stuebner:
>> Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
>>> +- clocks: from common clo
Heiko,
å¨ 09/02/2015 04:46 AM, Heiko Stuebner åé:
> Am Dienstag, 1. September 2015, 13:49:58 schrieb Yakir Yang:
>> Split the dp core driver from exynos directory to bridge
>> directory, and rename the core driver to analogix_dp_*,
>> leave the platform code
Hi Heiko,
å¨ 09/02/2015 12:51 AM, Heiko Stuebner åé:
> Am Dienstag, 1. September 2015, 14:04:15 schrieb Yakir Yang:
>> This phy driver would control the Rockchip DisplayPort module
>> phy clock and phy power, it is relate to analogix_dp-rockchip
>> dp driver. If you wan
Hi Heiko,
å¨ 2015/9/1 22:24, Heiko Stuebner åé:
> Am Dienstag, 1. September 2015, 14:01:28 schrieb Yakir Yang:
>> Rockchip have three clocks for dp controller, we leave pclk_edp
>> to analogix_dp driver control, and keep the sclk_edp_24m and
>> sclk_edp in platform dri
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Signed-off-by: Yakir Yang
---
Changes in v4:
- Call drm_panel_prepare() in .get_modes function, ensure panel
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Signed-off-by: Yakir Yang
---
Changes in v4:
- Take Jingoo suggest, add commit messages.
Changes in v3:
- move dp hpd det
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang
---
Changes in v4: None
Chang
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Signed-off-by: Yakir Yang
---
Changes in v4:
- Take Thierry suggest, seprate the link-rate and lane-count limit
out with the device_type flag.
Changes in v3
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error
drivers/gpu/drm/bridge/analogix
Signed-off-by: Yakir Yang
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Add GNU license v2 declared and samsung copyright
drivers/gpu/drm/exynos/exynos_dp.c | 1 +
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 1 +
include/drm/bridge/analogix_dp.h
This phy driver would control the Rockchip DisplayPort module
phy clock and phy power, it is relate to analogix_dp-rockchip
dp driver. If you want DP works rightly on rockchip platform,
then you should select both of them.
Signed-off-by: Yakir Yang
---
Changes in v4:
- Take Kishon suggest, add
From: Mark Yao
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao
Signed-off-by: Yakir Yang
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/gpu/drm
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang
---
Changes in v4:
- Remove some deprecated DT properties in rockchip dp document.
Changes in v3:
- Take Thierry
provide the backward compatibility, so there are no
bisectability break that make this change in a separate patch.
Signed-off-by: Yakir Yang
---
Changes in v4:
- Take Krzysztof suggest, separate all DTS changes to a separate patch.
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang
---
Changes in v4:
- Take Krzysztof
() in to achieve the compatibility hacks.
Signed-off-by: Yakir Yang
---
Changes in v4:
- Take Krzysztof suggest, provide backword compatibility with samsung.
- Take Thierry suggest, add "color-depth" and "color-space" dynamic parsed.
Changes in v3:
- Take Thierry Reding su
2Gbps, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang
---
Changes in v4:
- Take Jingoo Han suggest, update commit message more readable.
- Adjust the order from 05 to 04
Changes in v3:
- Take Thierry Reding suggest, link_rate and lane_count shouldn't config to
the DT property value directly,
Split the dp core driver from exynos directory to bridge
directory, and rename the core driver to analogix_dp_*,
leave the platform code to analogix_dp-exynos.
Signed-off-by: Yakir Yang
---
Changes in v4:
- Take Rob suggest, update "analogix,hpd-gpios" to "hpd-gpios" DT pr
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