[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 Alex Deucher changed: What|Removed |Added Status|NEW |RESOLVED Resolution|---

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #42 from equeim at gmail.com --- This patch fixed my issue of non-working UVD on cold boot. Thanks! -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #41 from Christian König --- (In reply to Alex Deucher from comment #40) > (In reply to Christian König from comment #39) > > Created attachment 113654 [details] [review] [review] > > Possible fix > > > > Wow, nice catch! > > > >

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #40 from Alex Deucher --- (In reply to Christian König from comment #39) > Created attachment 113654 [details] [review] > Possible fix > > Wow, nice catch! > > I have to admit that i just copied the sleep mode handling from previou

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 Christian König changed: What|Removed |Added CC||deathsimple at vodafone.de --- Commen

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #38 from Chernovsky Oleg --- I managed to make it work on my machine. I actually noticed that fglrx code never puts UPLL to sleep like we do. So I commented out all WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK); Aft

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #37 from Chernovsky Oleg --- Created attachment 113544 --> https://bugs.freedesktop.org/attachment.cgi?id=113544&action=edit fglrx mmiotrace dump (In reply to Christian König from comment #36) > Well it might already help if you p

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #36 from Christian König --- As Alex already noted the detailed register specs are unfortunately only available internally. We tried to have at least all the bit definitions needed by the driver documented in the header files, but s

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #35 from Alex Deucher --- (In reply to Chernovsky Oleg from comment #34) > > Is this some kind of open hardware docs? Or just internal? Maybe I missed > something Just internal. (In reply to Chernovsky Oleg from comment #33) > P.S.

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #34 from Chernovsky Oleg --- (In reply to Christian König from comment #32) > Strange, the hardware docs say this is for routing the reset signal and > shouldn't be touched by the driver, e.g. it should always be 1. Is this some ki

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #33 from Chernovsky Oleg --- Yep, I rechecked it and it seems set to 1 always... Anyway I gathered around 18 Mb of mmiotrace logs to investigate. Now digging through divider and clock registers. P.S. I only fear that maybe I launche

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #32 from Christian König --- (In reply to Chernovsky Oleg from comment #31) > Tried to launch vdpau-accelerated mpv with fglrx driver and mmiotrace. > Interesting, the CG_UPLL_FUNC_CNTL always has flags 0x100 | 0x600 > > R 4 456.556

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #31 from Chernovsky Oleg --- Tried to launch vdpau-accelerated mpv with fglrx driver and mmiotrace. Interesting, the CG_UPLL_FUNC_CNTL always has flags 0x100 | 0x600 R 4 456.556542 1 0xf634 0x707 0x0 0 W 4 456.556547 1 0xf634

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #30 from Christian König --- (In reply to Chernovsky Oleg from comment #29) > No luck. Tried various hacks and commenting return values. > > Will try mmiotracing these registers from fglrx on weekend Be careful that to write no irr

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #29 from Chernovsky Oleg --- No luck. Tried various hacks and commenting return values. Will try mmiotracing these registers from fglrx on weekend -- You are receiving this mail because: You are the assignee for the bug. --

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #28 from Chernovsky Oleg --- (In reply to Christian König from comment #27) > > > > [2.237380] [drm] At call 1 > > [3.278457] [drm] At call 2 > > [3.288474] [drm] Passed! > > Well just that I got it right: The first cal

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #27 from Christian König --- (In reply to Chernovsky Oleg from comment #25) > It's the first call to this function in si_set_uvd_clocks that's failing. > Doesn't work in bypass mode? Or maybe too low mdelay before call? > > [2.2

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #26 from Chernovsky Oleg --- Ah, forgot the last reg 0x648 0x (0) P.S. tried to increase wait delay with no success -- You are receiving this mail because: You are the assignee for the bug. -- next part -

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #25 from Chernovsky Oleg --- (In reply to Christian König from comment #24) > Now take a look at si_set_uvd_clocks in si.c. Especially try to figure out > if the first or the second call to radeon_uvd_send_upll_ctlreq fails. > > Add

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #24 from Christian König --- (In reply to Chernovsky Oleg from comment #23) > Wow! Pls forget my last comment completely. > > Just tried to watch H264 video and it was slow as hell :( Which is the espected result if you don't setup

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #23 from Chernovsky Oleg --- Wow! Pls forget my last comment completely. Just tried to watch H264 video and it was slow as hell :( Playing: Zoku Sayonara Zetsubou Sensei - 06.mkv [stream] Video (+) --vid=1 (h264) [stream] Audio (+)

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #22 from Chernovsky Oleg --- (In reply to Christian König from comment #20) It seems you were right, Christian, now I see [ 120.417486] [drm] UVD initialized successfully. I've played some videos using -vo=vdpau -hwdec=vdpau, all

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #21 from Chernovsky Oleg --- (In reply to Christian König from comment #20) > (In reply to Chernovsky Oleg from comment #15) > > I can help with code here. > > > > What should be implemented, roughly? > > Sounds good. I assume you

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #20 from Christian König --- (In reply to Chernovsky Oleg from comment #15) > I can help with code here. > > What should be implemented, roughly? Sounds good. I assume you got a card with that problem. First of all try if UVD work

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #19 from Alex Deucher --- (In reply to Chernovsky Oleg from comment #18) > Hm-m, just tried drm-next-3.20 branch and: > > [ 365.200918] [drm:radeon_uvd_send_upll_ctlreq [radeon]] *ERROR* Timeout > setting UVD clocks! > [ 365.200922

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #18 from Chernovsky Oleg --- (In reply to Alex Deucher from comment #16) > (In reply to Christian König from comment #14) > > (In reply to Öyvind Saether from comment #13) > > > on 3.18.1, could this be because the card is factory o

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #17 from Alex Deucher --- On older versions of the driver we init dpm after everything else, so the ring and ib tests happen before we even touch the dpm hw so clocks are at their low boot up levels. On newer versions of the driver w

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #16 from Alex Deucher --- (In reply to Christian König from comment #14) > (In reply to Öyvind Saether from comment #13) > > on 3.18.1, could this be because the card is factory overclocked? > > Yes, that's possible. If you activat

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #15 from Chernovsky Oleg --- I can help with code here. What should be implemented, roughly? -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was s

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #14 from Christian König --- (In reply to Öyvind Saether from comment #13) > on 3.18.1, could this be because the card is factory overclocked? Yes, that's possible. If you activate UVD you must downclock the system clock for it to

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 Öyvind Saether changed: What|Removed |Added CC||oyvinds at everdot.org --- Comment #13

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #12 from equeim at gmail.com --- Same on 3.18.0 -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment was scrubbed... URL:

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #11 from equeim at gmail.com --- I have the same issue with Radeon R9 280X. This happens only on cold boot. I've tried various kernels (3.14, 3.15, 3.17) without success. -- You are receiving this mail because: You are the assignee f

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #10 from sterfield at gmail.com --- Hi, I've got the exact same error, preventing me to use UVD for H264 decoding [ 12.836644] [drm] Enabling RC6 states: RC6 on, RC6p off, RC6pp off [ 12.878552] [drm:radeon_uvd_send_upll_ctlreq]

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #9 from sterfield at gmail.com --- Created attachment 107750 --> https://bugs.freedesktop.org/attachment.cgi?id=107750&action=edit dmesg Full dmesg after a cold boot, showing the UVD error. -- You are receiving this mail because:

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #8 from sterfield at gmail.com --- Created attachment 107749 --> https://bugs.freedesktop.org/attachment.cgi?id=107749&action=edit lspci of my graphic card This is a result of "lspci -s 01:00.0 -vvv", showing all the details of my g

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #7 from ?yvind Saether --- > Can you bisect? Not sure how to do that but if you want to point me to some instructions then please do. Basically suspend and resume works with 3.12 kernels but in later kernels I can suspend and then r

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #6 from Alex Deucher --- (In reply to comment #5) > > also, suspend and resume does not work with 3.13 and 3.14 but works with > 3.12 but I haz no clue if this has anything to do with radeon but those > errors ^^ are present in this

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #5 from ?yvind Saether --- 01:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Pitcairn PRO [Radeon HD 7850] 3.14.2-gentoo [2.360636] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks! [

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #4 from Alex Deucher --- (In reply to comment #3) > same problem here. UVD is initialised properly but setting clocks timesout. If this is a regression, can you bisect? -- You are receiving this mail because: You are the assignee f

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #3 from glphvgacs --- same problem here. UVD is initialised properly but setting clocks timesout. -- You are receiving this mail because: You are the assignee for the bug. -- next part -- An HTML attachment w

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #2 from glphvgacs --- Created attachment 96253 --> https://bugs.freedesktop.org/attachment.cgi?id=96253&action=edit full-dmesg grep for uvd_send -- You are receiving this mail because: You are the assignee for the bug. --

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 --- Comment #1 from Christian K?nig --- Please double check that your hardware isn't overheating. Did you changed anything on the timing parameters (Over-clocking tools etc...)? Cause the clocks for UVD mode look a bit odd. -- You are receivin

[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

https://bugs.freedesktop.org/show_bug.cgi?id=73378 Christian K?nig changed: What|Removed |Added Summary|[radeonsi] uvd cannot |[drm:radeon_uvd_send_upll_c