Re: [PATCH] drm/msm/adreno: De-spaghettify the use of memory barriers

2024-06-25 Thread Akhil P Oommen
On Tue, Jun 18, 2024 at 10:08:23PM +0530, Akhil P Oommen wrote: > On Tue, Jun 04, 2024 at 07:35:04PM +0200, Konrad Dybcio wrote: > > > > > > On 5/14/24 20:38, Akhil P Oommen wrote: > > > On Wed, May 08, 2024 at 07:46:31PM +0200, Konrad Dybcio wrote: > > > > Memory barriers help ensure

Re: [PATCH] drm/msm/adreno: De-spaghettify the use of memory barriers

2024-06-25 Thread Akhil P Oommen
On Thu, Jun 20, 2024 at 02:04:01PM +0100, Will Deacon wrote: > On Tue, Jun 18, 2024 at 09:41:58PM +0530, Akhil P Oommen wrote: > > On Tue, Jun 04, 2024 at 03:40:56PM +0100, Will Deacon wrote: > > > On Thu, May 16, 2024 at 01:55:26PM -0500, Andrew Halaney wrote: > > > > On Thu, May 16, 2024 at

Re: [PATCH] drm/msm/adreno: De-spaghettify the use of memory barriers

2024-06-20 Thread Will Deacon
On Tue, Jun 18, 2024 at 09:41:58PM +0530, Akhil P Oommen wrote: > On Tue, Jun 04, 2024 at 03:40:56PM +0100, Will Deacon wrote: > > On Thu, May 16, 2024 at 01:55:26PM -0500, Andrew Halaney wrote: > > > On Thu, May 16, 2024 at 08:20:05PM GMT, Akhil P Oommen wrote: > > > > On Thu, May 16, 2024 at

Re: [PATCH] drm/msm/adreno: De-spaghettify the use of memory barriers

2024-06-18 Thread Akhil P Oommen
On Tue, Jun 04, 2024 at 07:35:04PM +0200, Konrad Dybcio wrote: > > > On 5/14/24 20:38, Akhil P Oommen wrote: > > On Wed, May 08, 2024 at 07:46:31PM +0200, Konrad Dybcio wrote: > > > Memory barriers help ensure instruction ordering, NOT time and order > > > of actual write arrival at other

Re: [PATCH] drm/msm/adreno: De-spaghettify the use of memory barriers

2024-06-18 Thread Akhil P Oommen
On Tue, Jun 04, 2024 at 03:40:56PM +0100, Will Deacon wrote: > On Thu, May 16, 2024 at 01:55:26PM -0500, Andrew Halaney wrote: > > On Thu, May 16, 2024 at 08:20:05PM GMT, Akhil P Oommen wrote: > > > On Thu, May 16, 2024 at 08:15:34AM -0500, Andrew Halaney wrote: > > > > If I understand correctly,

Re: [PATCH] drm/msm/adreno: De-spaghettify the use of memory barriers

2024-06-18 Thread Will Deacon
On Thu, Jun 06, 2024 at 02:03:24PM +0200, Konrad Dybcio wrote: > On 4.06.2024 4:40 PM, Will Deacon wrote: > > On Thu, May 16, 2024 at 01:55:26PM -0500, Andrew Halaney wrote: > >> On Thu, May 16, 2024 at 08:20:05PM GMT, Akhil P Oommen wrote: > >>> On Thu, May 16, 2024 at 08:15:34AM -0500, Andrew

Re: [PATCH] drm/msm/adreno: De-spaghettify the use of memory barriers

2024-06-06 Thread Konrad Dybcio
On 4.06.2024 4:40 PM, Will Deacon wrote: > On Thu, May 16, 2024 at 01:55:26PM -0500, Andrew Halaney wrote: >> On Thu, May 16, 2024 at 08:20:05PM GMT, Akhil P Oommen wrote: >>> On Thu, May 16, 2024 at 08:15:34AM -0500, Andrew Halaney wrote: If I understand correctly, you don't need any memory

Re: [PATCH] drm/msm/adreno: De-spaghettify the use of memory barriers

2024-06-04 Thread Konrad Dybcio
On 5/14/24 20:38, Akhil P Oommen wrote: On Wed, May 08, 2024 at 07:46:31PM +0200, Konrad Dybcio wrote: Memory barriers help ensure instruction ordering, NOT time and order of actual write arrival at other observers (e.g. memory-mapped IP). On architectures employing weak memory ordering, the

Re: [PATCH] drm/msm/adreno: De-spaghettify the use of memory barriers

2024-06-04 Thread Will Deacon
On Thu, May 16, 2024 at 01:55:26PM -0500, Andrew Halaney wrote: > On Thu, May 16, 2024 at 08:20:05PM GMT, Akhil P Oommen wrote: > > On Thu, May 16, 2024 at 08:15:34AM -0500, Andrew Halaney wrote: > > > If I understand correctly, you don't need any memory barrier. > > > writel()/readl()'s are

Re: [PATCH] drm/msm/adreno: De-spaghettify the use of memory barriers

2024-05-16 Thread Andrew Halaney
On Thu, May 16, 2024 at 08:20:05PM GMT, Akhil P Oommen wrote: > On Thu, May 16, 2024 at 08:15:34AM -0500, Andrew Halaney wrote: > > On Wed, May 15, 2024 at 12:08:49AM GMT, Akhil P Oommen wrote: > > > On Wed, May 08, 2024 at 07:46:31PM +0200, Konrad Dybcio wrote: > > > > Memory barriers help ensure

Re: [PATCH] drm/msm/adreno: De-spaghettify the use of memory barriers

2024-05-16 Thread Akhil P Oommen
On Thu, May 16, 2024 at 08:15:34AM -0500, Andrew Halaney wrote: > On Wed, May 15, 2024 at 12:08:49AM GMT, Akhil P Oommen wrote: > > On Wed, May 08, 2024 at 07:46:31PM +0200, Konrad Dybcio wrote: > > > Memory barriers help ensure instruction ordering, NOT time and order > > > of actual write

Re: [PATCH] drm/msm/adreno: De-spaghettify the use of memory barriers

2024-05-16 Thread Andrew Halaney
On Wed, May 15, 2024 at 12:08:49AM GMT, Akhil P Oommen wrote: > On Wed, May 08, 2024 at 07:46:31PM +0200, Konrad Dybcio wrote: > > Memory barriers help ensure instruction ordering, NOT time and order > > of actual write arrival at other observers (e.g. memory-mapped IP). > > On architectures

Re: [PATCH] drm/msm/adreno: De-spaghettify the use of memory barriers

2024-05-14 Thread Akhil P Oommen
On Wed, May 08, 2024 at 07:46:31PM +0200, Konrad Dybcio wrote: > Memory barriers help ensure instruction ordering, NOT time and order > of actual write arrival at other observers (e.g. memory-mapped IP). > On architectures employing weak memory ordering, the latter can be a > giant pain point, and

[PATCH] drm/msm/adreno: De-spaghettify the use of memory barriers

2024-05-08 Thread Konrad Dybcio
Memory barriers help ensure instruction ordering, NOT time and order of actual write arrival at other observers (e.g. memory-mapped IP). On architectures employing weak memory ordering, the latter can be a giant pain point, and it has been as part of this driver. Moreover, the gpu_/gmu_ accessors