[PATCH 0/3] refactor some ldb related clocks

2013-08-21 Thread Liu Ying
On 08/21/2013 09:59 AM, Shawn Guo wrote: > Hi Ying, > > On Tue, Aug 20, 2013 at 06:08:48PM +0800, Liu Ying wrote: >>> While I admit to having introduced the combination of 1/3.5 fixed >>> divider and configurable 1/1,1/2 divder clocks to describe this >>> fractional divider for the reasons you

[PATCH 0/3] refactor some ldb related clocks

2013-08-21 Thread Shawn Guo
Hi Ying, On Tue, Aug 20, 2013 at 06:08:48PM +0800, Liu Ying wrote: > > While I admit to having introduced the combination of 1/3.5 fixed > > divider and configurable 1/1,1/2 divder clocks to describe this > > fractional divider for the reasons you state, I think the correct > > solution would be

[PATCH 0/3] refactor some ldb related clocks

2013-08-20 Thread Liu Ying
On 08/20/2013 05:43 PM, Philipp Zabel wrote: > Am Dienstag, den 20.08.2013, 16:38 +0800 schrieb Liu Ying: >> The ldb_di[0/1]_ipu_div clock dividers in the CSCMR2 register >> of i.MX53, i.MX6Q and i.MX6DL SoCs can be configured to a 1/3.5 >> drivider or a 1/7 divider. The common clock framework

[PATCH 0/3] refactor some ldb related clocks

2013-08-20 Thread Liu Ying
The ldb_di[0/1]_ipu_div clock dividers in the CSCMR2 register of i.MX53, i.MX6Q and i.MX6DL SoCs can be configured to a 1/3.5 drivider or a 1/7 divider. The common clock framework cannot deal with the two dividers directly even with the divider table which only supports integral dividers. So, the

[PATCH 0/3] refactor some ldb related clocks

2013-08-20 Thread Philipp Zabel
Am Dienstag, den 20.08.2013, 16:38 +0800 schrieb Liu Ying: > The ldb_di[0/1]_ipu_div clock dividers in the CSCMR2 register > of i.MX53, i.MX6Q and i.MX6DL SoCs can be configured to a 1/3.5 > drivider or a 1/7 divider. The common clock framework cannot > deal with the two dividers directly even

[PATCH 0/3] refactor some ldb related clocks

2013-08-20 Thread Liu Ying
The ldb_di[0/1]_ipu_div clock dividers in the CSCMR2 register of i.MX53, i.MX6Q and i.MX6DL SoCs can be configured to a 1/3.5 drivider or a 1/7 divider. The common clock framework cannot deal with the two dividers directly even with the divider table which only supports integral dividers. So, the

Re: [PATCH 0/3] refactor some ldb related clocks

2013-08-20 Thread Philipp Zabel
Am Dienstag, den 20.08.2013, 16:38 +0800 schrieb Liu Ying: The ldb_di[0/1]_ipu_div clock dividers in the CSCMR2 register of i.MX53, i.MX6Q and i.MX6DL SoCs can be configured to a 1/3.5 drivider or a 1/7 divider. The common clock framework cannot deal with the two dividers directly even with

Re: [PATCH 0/3] refactor some ldb related clocks

2013-08-20 Thread Liu Ying
On 08/20/2013 05:43 PM, Philipp Zabel wrote: Am Dienstag, den 20.08.2013, 16:38 +0800 schrieb Liu Ying: The ldb_di[0/1]_ipu_div clock dividers in the CSCMR2 register of i.MX53, i.MX6Q and i.MX6DL SoCs can be configured to a 1/3.5 drivider or a 1/7 divider. The common clock framework cannot

Re: [PATCH 0/3] refactor some ldb related clocks

2013-08-20 Thread Shawn Guo
Hi Ying, On Tue, Aug 20, 2013 at 06:08:48PM +0800, Liu Ying wrote: While I admit to having introduced the combination of 1/3.5 fixed divider and configurable 1/1,1/2 divder clocks to describe this fractional divider for the reasons you state, I think the correct solution would be to

Re: [PATCH 0/3] refactor some ldb related clocks

2013-08-20 Thread Liu Ying
On 08/21/2013 09:59 AM, Shawn Guo wrote: Hi Ying, On Tue, Aug 20, 2013 at 06:08:48PM +0800, Liu Ying wrote: While I admit to having introduced the combination of 1/3.5 fixed divider and configurable 1/1,1/2 divder clocks to describe this fractional divider for the reasons you state, I think