On Fri, May 31, 2024 at 03:29:06PM +0800, Chen-Yu Tsai wrote:
> On Thu, May 30, 2024 at 11:43 PM Conor Dooley wrote:
> >
> > On Thu, May 30, 2024 at 04:35:00PM +0800, Chen-Yu Tsai wrote:
> > > +#include
> > > +#include
> > > +
> > > +mfgtop: clock-controller@13fff000 {
>
On Thu, May 30, 2024 at 11:43 PM Conor Dooley wrote:
>
> On Thu, May 30, 2024 at 04:35:00PM +0800, Chen-Yu Tsai wrote:
> > The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP
> > in the datasheet, that contains clock gates, some power sequence signal
> > delays, and other
On Thu, May 30, 2024 at 04:35:00PM +0800, Chen-Yu Tsai wrote:
> The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP
> in the datasheet, that contains clock gates, some power sequence signal
> delays, and other unknown registers that get toggled when the GPU is
> powered on.
>
The MFG (GPU) block on the MT8173 has a small glue layer, named MFG_TOP
in the datasheet, that contains clock gates, some power sequence signal
delays, and other unknown registers that get toggled when the GPU is
powered on.
The clock gates are exposed as clocks provided by a clock controller,
