On Fri, May 17, 2019 at 05:37:22PM +0100, Robin Murphy wrote:
> On the Arm Juno platform, the HDLCD pixel clock is constrained to 250KHz
> resolution in order to avoid the tiny System Control Processor spending
> aeons trying to calculate exact PLL coefficients. This means that modes
> like my
On the Arm Juno platform, the HDLCD pixel clock is constrained to 250KHz
resolution in order to avoid the tiny System Control Processor spending
aeons trying to calculate exact PLL coefficients. This means that modes
like my oddball 1600x1200 with 130.89MHz clock get rejected since the
rate cannot
