On Wed, Jun 5, 2024 at 7:25 PM AngeloGioacchino Del Regno
wrote:
>
> Il 05/06/24 10:25, Chen-Yu Tsai ha scritto:
> > On Thu, May 30, 2024 at 6:03 PM AngeloGioacchino Del Regno
> > wrote:
> >>
> >> Il 30/05/24 10:35, Chen-Yu Tsai ha scritto:
> >>> The MFG_ASYNC domain, which is likely associated t
Il 05/06/24 10:25, Chen-Yu Tsai ha scritto:
On Thu, May 30, 2024 at 6:03 PM AngeloGioacchino Del Regno
wrote:
Il 30/05/24 10:35, Chen-Yu Tsai ha scritto:
The MFG_ASYNC domain, which is likely associated to the whole MFG block,
currently specifies clk26m as its domain clock. This is bogus, sin
On Thu, May 30, 2024 at 6:03 PM AngeloGioacchino Del Regno
wrote:
>
> Il 30/05/24 10:35, Chen-Yu Tsai ha scritto:
> > The MFG_ASYNC domain, which is likely associated to the whole MFG block,
> > currently specifies clk26m as its domain clock. This is bogus, since the
> > clock is an external cryst
Il 30/05/24 10:35, Chen-Yu Tsai ha scritto:
The MFG_ASYNC domain, which is likely associated to the whole MFG block,
currently specifies clk26m as its domain clock. This is bogus, since the
clock is an external crystal with no controls. Also, the MFG block has
a independent CLK_TOP_AXI_MFG_IN_SEL
The MFG_ASYNC domain, which is likely associated to the whole MFG block,
currently specifies clk26m as its domain clock. This is bogus, since the
clock is an external crystal with no controls. Also, the MFG block has
a independent CLK_TOP_AXI_MFG_IN_SEL clock, which according to the block
diagram,
