On 3/3/22 13:54, Maxime Ripard wrote:
[...]
Regarding the default value -- there are no in-tree users of this driver yet
(per git grep in current linux-next), do we really care about backward
compatibility in this case?
If it hasn't been in a stable release yet, no. If it did, yes
It was
On Wed, Mar 02, 2022 at 04:17:04PM +0100, Marek Vasut wrote:
> On 3/2/22 11:01, Maxime Ripard wrote:
> > On Thu, Feb 17, 2022 at 01:25:22AM +0100, Marek Vasut wrote:
> > > The driver currently hard-codes DSI lane count to two, however the chip
> > > is capable of operating in 1..4 DSI lanes mode.
On 3/2/22 11:01, Maxime Ripard wrote:
On Thu, Feb 17, 2022 at 01:25:22AM +0100, Marek Vasut wrote:
The driver currently hard-codes DSI lane count to two, however the chip
is capable of operating in 1..4 DSI lanes mode. Parse 'data-lanes' DT
property and program the result into DSI_CTRL
On Thu, Feb 17, 2022 at 01:25:22AM +0100, Marek Vasut wrote:
> The driver currently hard-codes DSI lane count to two, however the chip
> is capable of operating in 1..4 DSI lanes mode. Parse 'data-lanes' DT
> property and program the result into DSI_CTRL register.
>
> Signed-off-by: Marek Vasut
The driver currently hard-codes DSI lane count to two, however the chip
is capable of operating in 1..4 DSI lanes mode. Parse 'data-lanes' DT
property and program the result into DSI_CTRL register.
Signed-off-by: Marek Vasut
Cc: Jagan Teki
Cc: Maxime Ripard
Cc: Robert Foss
Cc: Sam Ravnborg
