Re: [PATCH v1] drm/msm/dpu: improve DSC allocation

2023-12-04 Thread Dmitry Baryshkov
On Mon, 4 Dec 2023 at 18:37, Kuogee Hsieh wrote: > > > On 11/29/2023 7:57 PM, Dmitry Baryshkov wrote: > > On Wed, 29 Nov 2023 at 22:31, Kuogee Hsieh wrote: > >> A DCE (Display Compression Engine) contains two DSC hard slice encoders. > >> Each DCE start with even DSC encoder index followed by an

Re: [PATCH v1] drm/msm/dpu: improve DSC allocation

2023-12-04 Thread Kuogee Hsieh
On 11/29/2023 7:57 PM, Dmitry Baryshkov wrote: On Wed, 29 Nov 2023 at 22:31, Kuogee Hsieh wrote: A DCE (Display Compression Engine) contains two DSC hard slice encoders. Each DCE start with even DSC encoder index followed by an odd DSC encoder index. Each encoder can work independently. But

Re: [PATCH v1] drm/msm/dpu: improve DSC allocation

2023-11-30 Thread kernel test robot
-DSC-allocation/20231130-064646 base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next patch link: https://lore.kernel.org/r/1701289898-12235-1-git-send-email-quic_khsieh%40quicinc.com patch subject: [PATCH v1] drm/msm/dpu: improve DSC allocation config: arm-defconfig (https

Re: [PATCH v1] drm/msm/dpu: improve DSC allocation

2023-11-30 Thread kernel test robot
-allocation/20231130-064646 base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next patch link: https://lore.kernel.org/r/1701289898-12235-1-git-send-email-quic_khsieh%40quicinc.com patch subject: [PATCH v1] drm/msm/dpu: improve DSC allocation config: powerpc-allmodconfig (https

Re: [PATCH v1] drm/msm/dpu: improve DSC allocation

2023-11-30 Thread kernel test robot
-DSC-allocation/20231130-064646 base: git://anongit.freedesktop.org/drm/drm-misc drm-misc-next patch link: https://lore.kernel.org/r/1701289898-12235-1-git-send-email-quic_khsieh%40quicinc.com patch subject: [PATCH v1] drm/msm/dpu: improve DSC allocation config: arm64-defconfig (https

Re: [PATCH v1] drm/msm/dpu: improve DSC allocation

2023-11-29 Thread Dmitry Baryshkov
On Wed, 29 Nov 2023 at 22:31, Kuogee Hsieh wrote: > > A DCE (Display Compression Engine) contains two DSC hard slice encoders. > Each DCE start with even DSC encoder index followed by an odd DSC encoder > index. Each encoder can work independently. But Only two DSC encoders from > same DCE can be

[PATCH v1] drm/msm/dpu: improve DSC allocation

2023-11-29 Thread Kuogee Hsieh
A DCE (Display Compression Engine) contains two DSC hard slice encoders. Each DCE start with even DSC encoder index followed by an odd DSC encoder index. Each encoder can work independently. But Only two DSC encoders from same DCE can be paired to work together to support merge mode. In addition,