Hi,
Am Sonntag, dem 25.06.2023 um 11:51 +0800 schrieb Sui Jingfeng:
> Hi,
>
> On 2023/6/22 01:45, Lucas Stach wrote:
> > Am Donnerstag, dem 22.06.2023 um 01:21 +0800 schrieb Sui Jingfeng:
> > > Hi,
> > >
> > > On 2023/6/21 23:58, Lucas Stach wrote:
> > > > Am Mittwoch, dem 21.06.2023 um 23:30 +0
Hi,
On 2023/6/22 01:53, Lucas Stach wrote:
Am Donnerstag, dem 22.06.2023 um 01:31 +0800 schrieb Sui Jingfeng:
Hi,
On 2023/6/22 00:07, Lucas Stach wrote:
And as the HW guarantees it on your platform, your platform
implementation makes this function effectively a no-op. Skipping the
call to thi
Hi,
On 2023/6/22 01:45, Lucas Stach wrote:
Am Donnerstag, dem 22.06.2023 um 01:21 +0800 schrieb Sui Jingfeng:
Hi,
On 2023/6/21 23:58, Lucas Stach wrote:
Am Mittwoch, dem 21.06.2023 um 23:30 +0800 schrieb Sui Jingfeng:
Hi,
On 2023/6/21 18:00, Lucas Stach wrote:
dma_sync_sgta
Hi,
On 2023/6/22 01:45, Lucas Stach wrote:
Again,
this is user-space things!
this is user-space things!
this is user-space things!
I have explained several times.
made the decision for the user-space program is wrong.
This mode of communication isn't helpful. Please stop it.
As I tried t
Hi,
On 2023/6/23 19:52, Robin Murphy wrote:
On 2023-06-20 10:47, Sui Jingfeng wrote:
From: Sui Jingfeng
Loongson CPUs maintain cache coherency by hardware, which means that the
data in the CPU cache is identical to the data in main system memory. As
for the peripheral device, most of Loongson
On 2023-06-20 10:47, Sui Jingfeng wrote:
From: Sui Jingfeng
Loongson CPUs maintain cache coherency by hardware, which means that the
data in the CPU cache is identical to the data in main system memory. As
for the peripheral device, most of Loongson chips chose to define the
peripherals as DMA
Hi
On 2023/6/21 23:58, Lucas Stach wrote:
Am Mittwoch, dem 21.06.2023 um 23:30 +0800 schrieb Sui Jingfeng:
Hi,
On 2023/6/21 18:00, Lucas Stach wrote:
dma_sync_sgtable_for_cpu(dev->dev, etnaviv_obj->sgt,
etnaviv_op_to_dma_dir(op));
Am Donnerstag, dem 22.06.2023 um 01:31 +0800 schrieb Sui Jingfeng:
> Hi,
>
> On 2023/6/22 00:07, Lucas Stach wrote:
> > And as the HW guarantees it on your platform, your platform
> > implementation makes this function effectively a no-op. Skipping the
> > call to this function is breaking the DMA
Am Donnerstag, dem 22.06.2023 um 01:21 +0800 schrieb Sui Jingfeng:
> Hi,
>
> On 2023/6/21 23:58, Lucas Stach wrote:
> > Am Mittwoch, dem 21.06.2023 um 23:30 +0800 schrieb Sui Jingfeng:
> > > Hi,
> > >
> > > On 2023/6/21 18:00, Lucas Stach wrote:
> > > > > dma_sync_sgtable_for_cpu(de
Hi,
On 2023/6/22 00:07, Lucas Stach wrote:
And as the HW guarantees it on your platform, your platform
implementation makes this function effectively a no-op. Skipping the
call to this function is breaking the DMA API abstraction, as now the
driver is second guessing the DMA API implementation.
Hi,
On 2023/6/21 23:58, Lucas Stach wrote:
Am Mittwoch, dem 21.06.2023 um 23:30 +0800 schrieb Sui Jingfeng:
Hi,
On 2023/6/21 18:00, Lucas Stach wrote:
dma_sync_sgtable_for_cpu(dev->dev, etnaviv_obj->sgt,
etnaviv_op_to_dma_dir(op));
Hi
On 2023/6/21 23:58, Lucas Stach wrote:
you approach forbidden any possibility to use the WC BO at anywhere.
My approach need only check once, while you approach need at least 3
check plus
so much bit-wise logic operations, plus a function call (&, ==, &&,
&, ~, &) .
and every time you c
Hi,
On 2023/6/22 00:12, Lucas Stach wrote:
Am Mittwoch, dem 21.06.2023 um 23:41 +0800 schrieb Sui Jingfeng:
On 2023/6/21 23:23, Lucas Stach wrote:
Am Mittwoch, dem 21.06.2023 um 22:44 +0800 schrieb Sui Jingfeng:
Hi,
On 2023/6/21 18:00, Lucas Stach wrote:
diff --git a/drivers/gpu/drm/etnaviv
Hi,
On 2023/6/22 00:12, Lucas Stach wrote:
Am Mittwoch, dem 21.06.2023 um 23:41 +0800 schrieb Sui Jingfeng:
On 2023/6/21 23:23, Lucas Stach wrote:
Am Mittwoch, dem 21.06.2023 um 22:44 +0800 schrieb Sui Jingfeng:
Hi,
On 2023/6/21 18:00, Lucas Stach wrote:
diff --git a/drivers/gpu/drm/etnaviv
Am Mittwoch, dem 21.06.2023 um 23:41 +0800 schrieb Sui Jingfeng:
> On 2023/6/21 23:23, Lucas Stach wrote:
> > Am Mittwoch, dem 21.06.2023 um 22:44 +0800 schrieb Sui Jingfeng:
> > > Hi,
> > >
> > > On 2023/6/21 18:00, Lucas Stach wrote:
> > > > > diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.h
Am Mittwoch, dem 21.06.2023 um 23:54 +0800 schrieb Sui Jingfeng:
> Hi,
>
> On 2023/6/21 23:33, Lucas Stach wrote:
> > Am Mittwoch, dem 21.06.2023 um 23:00 +0800 schrieb Sui Jingfeng:
> > > On 2023/6/21 18:00, Lucas Stach wrote:
> > > > >static inline enum dma_data_direction etnaviv_op_to_dma_d
Am Mittwoch, dem 21.06.2023 um 23:30 +0800 schrieb Sui Jingfeng:
> Hi,
>
> On 2023/6/21 18:00, Lucas Stach wrote:
> > > dma_sync_sgtable_for_cpu(dev->dev, etnaviv_obj->sgt,
> > >etnaviv_op_to_dma_dir(op));
> > > etnavi
Hi,
On 2023/6/21 23:33, Lucas Stach wrote:
Am Mittwoch, dem 21.06.2023 um 23:00 +0800 schrieb Sui Jingfeng:
On 2023/6/21 18:00, Lucas Stach wrote:
static inline enum dma_data_direction etnaviv_op_to_dma_dir(u32 op)
@@ -369,6 +381,7 @@ int etnaviv_gem_cpu_prep(struct drm_gem_object *obj, u32
On 2023/6/21 23:23, Lucas Stach wrote:
Am Mittwoch, dem 21.06.2023 um 22:44 +0800 schrieb Sui Jingfeng:
Hi,
On 2023/6/21 18:00, Lucas Stach wrote:
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.h
b/drivers/gpu/drm/etnaviv/etnaviv_drv.h
index 9cd72948cfad..644e5712c050 100644
--- a/drivers
Am Mittwoch, dem 21.06.2023 um 23:00 +0800 schrieb Sui Jingfeng:
> On 2023/6/21 18:00, Lucas Stach wrote:
> > > static inline enum dma_data_direction etnaviv_op_to_dma_dir(u32 op)
> > > @@ -369,6 +381,7 @@ int etnaviv_gem_cpu_prep(struct drm_gem_object *obj,
> > > u32 op,
> > > {
> > >
Hi,
On 2023/6/21 18:00, Lucas Stach wrote:
dma_sync_sgtable_for_cpu(dev->dev, etnaviv_obj->sgt,
etnaviv_op_to_dma_dir(op));
etnaviv_obj->last_cpu_prep_op = op;
@@ -408,8 +421,9 @@ int etnaviv_gem_cpu_fini(struct drm_gem_obj
Am Mittwoch, dem 21.06.2023 um 22:44 +0800 schrieb Sui Jingfeng:
> Hi,
>
> On 2023/6/21 18:00, Lucas Stach wrote:
> > > diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.h
> > > b/drivers/gpu/drm/etnaviv/etnaviv_drv.h
> > > index 9cd72948cfad..644e5712c050 100644
> > > --- a/drivers/gpu/drm/etnavi
On 2023/6/21 18:00, Lucas Stach wrote:
static inline enum dma_data_direction etnaviv_op_to_dma_dir(u32 op)
@@ -369,6 +381,7 @@ int etnaviv_gem_cpu_prep(struct drm_gem_object *obj, u32 op,
{
struct etnaviv_gem_object *etnaviv_obj = to_etnaviv_bo(obj);
struct drm_device *dev =
Hi
On 2023/6/21 18:00, Lucas Stach wrote:
+ case ETNA_BO_CACHED:
+ prot = PAGE_KERNEL;
+ break;
+ case ETNA_BO_UNCACHED:
+ prot = pgprot_noncached(PAGE_KERNEL);
+ break;
+ case ETNA_BO_WC:
+ default:
+
On 2023/6/21 18:00, Lucas Stach wrote:
/* list of GEM objects: */
struct mutex gem_lock;
struct list_head gem_list;
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem.c
b/drivers/gpu/drm/etnaviv/etnaviv_gem.c
index b5f73502e3dd..39bdc3774f2d 100644
--- a/drivers/gpu/drm/e
Hi,
On 2023/6/21 18:00, Lucas Stach wrote:
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.h
b/drivers/gpu/drm/etnaviv/etnaviv_drv.h
index 9cd72948cfad..644e5712c050 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_drv.h
+++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.h
@@ -46,6 +46,12 @@ struct etnaviv
On 2023/6/21 18:00, Lucas Stach wrote:
+static bool etnaviv_is_dma_coherent(struct device *dev)
+{
+ struct device_node *np;
+ bool coherent;
+
+ np = etnaviv_of_first_available_node();
+ if (np) {
+ coherent = of_dma_is_coherent(np);
+ of_nod
From: Sui Jingfeng
Loongson CPUs maintain cache coherency by hardware, which means that the
data in the CPU cache is identical to the data in main system memory. As
for the peripheral device, most of Loongson chips chose to define the
peripherals as DMA coherent by default, device drivers do not
Am Dienstag, dem 20.06.2023 um 17:47 +0800 schrieb Sui Jingfeng:
> From: Sui Jingfeng
>
> Loongson CPUs maintain cache coherency by hardware, which means that the
> data in the CPU cache is identical to the data in main system memory. As
> for the peripheral device, most of Loongson chips chose t
Loongson CPUs maintain cache coherency by hardware, which means that the
data in the CPU cache is identical to the data in main system memory. As
for the peripheral device, most of Loongson chips chose to define the
peripherals as DMA coherent by default, device drivers do not need to
maintain the
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