Hi,
On Wed, Apr 08, 2020 at 07:32:58PM +0200, Sam Ravnborg wrote:
> Hi Guido.
>
> We discussed this binding briefly on IRC:
>
> 19:28 port 0 is defined as
> 19:28 + Input port node to receive pixel data from the
> 19:28 + display controller. Exactly one endpoint must be
>
Hi Guido.
We discussed this binding briefly on IRC:
19:28 port 0 is defined as
19:28 + Input port node to receive pixel data from the
19:28 + display controller. Exactly one endpoint must be
19:28 + specified.
19:28 then there's two endpoints,
On Fri, Mar 20,
On Fri, Mar 20, 2020 at 3:49 PM Guido Günther wrote:
>
> The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs.
>
> Signed-off-by: Guido Günther
> Tested-by: Robert Chiras
> Reviewed-by: Rob Herring
> Acked-by: Sam Ravnborg
Reviewed-by: Fabio Estevam
The Northwest Logic MIPI DSI IP core can be found in NXPs i.MX8 SoCs.
Signed-off-by: Guido Günther
Tested-by: Robert Chiras
Reviewed-by: Rob Herring
Acked-by: Sam Ravnborg
---
.../bindings/display/bridge/nwl-dsi.yaml | 216 ++
1 file changed, 216 insertions(+)
create
