On 2016-08-31 23:42, Meng Yi wrote:
> Hi Stefan,
>
> Could you test this patch on vf610, I think it will woks fine.
See comment below.
>
> When could you merge this path? And how about the patches for gamma
> correction and multi-layer support by the way?
Still need to look in those patches. I
Hi Stefan,
Could you test this patch on vf610, I think it will woks fine.
When could you merge this path? And how about the patches for gamma correction
and multi-layer support by the way?
Best Regards,
Meng
> > > diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
> > > b/drivers/gpu/drm/f
> > drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
> > b/drivers/gpu/drm/fsl- dcu/fsl_dcu_drm_drv.c index 7882387..a590ce8
> > 100644
> > --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_
> drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c b/drivers/gpu/drm/fsl-
> dcu/fsl_dcu_drm_drv.c
> index 7882387..a590ce8 100644
> --- a/drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
> +++ b
While clk_register_divider will write register as little endian,
Modified the param "shift" from 0 to 24 since DCU is big endian.
Or reg "DCU_DIV_RATIO" will be seted as a incorrect value which
will cause vblank timing issue etc.
Signed-off-by: Meng Yi
---
Changes in V2:
-check the soc name to de
