On 02/08/2017 08:19 AM, Daniel Vetter wrote:
> On Wed, Feb 8, 2017 at 6:19 AM, Stefan Agner wrote:
>> On 2016-12-14 13:25, Marek Vasut wrote:
>>> On 12/14/2016 09:48 PM, Stefan Agner wrote:
The DRM subsystem specifies the pixel clock polarity from a
controllers perspective: DRM_BUS_FLAG_
On Wed, Feb 8, 2017 at 6:19 AM, Stefan Agner wrote:
> On 2016-12-14 13:25, Marek Vasut wrote:
>> On 12/14/2016 09:48 PM, Stefan Agner wrote:
>>> The DRM subsystem specifies the pixel clock polarity from a
>>> controllers perspective: DRM_BUS_FLAG_PIXDATA_NEGEDGE means
>>> the controller drives the
Dave, Marek,
On 2016-12-14 13:25, Marek Vasut wrote:
> On 12/14/2016 09:48 PM, Stefan Agner wrote:
>> The DRM subsystem specifies the pixel clock polarity from a
>> controllers perspective: DRM_BUS_FLAG_PIXDATA_NEGEDGE means
>> the controller drives the data on pixel clocks falling edge.
>> That i
On 12/14/2016 09:48 PM, Stefan Agner wrote:
> The DRM subsystem specifies the pixel clock polarity from a
> controllers perspective: DRM_BUS_FLAG_PIXDATA_NEGEDGE means
> the controller drives the data on pixel clocks falling edge.
> That is the controllers DOTCLK_POL=0 (Default is data launched
> a
The DRM subsystem specifies the pixel clock polarity from a
controllers perspective: DRM_BUS_FLAG_PIXDATA_NEGEDGE means
the controller drives the data on pixel clocks falling edge.
That is the controllers DOTCLK_POL=0 (Default is data launched
at negative edge).
Also change the data enable logic t