On 1/11/21 6:20 PM, Maxime Ripard wrote:
On Fri, Jan 08, 2021 at 03:34:52PM +0100, Giulio Benetti wrote:
Hi,
On 1/8/21 10:23 AM, Maxime Ripard wrote:
Hi,
Thanks for those patches
On Thu, Jan 07, 2021 at 03:30:32AM +0100, Giulio Benetti wrote:
From: Giulio Benetti
It turned out(Maxime sugg
On Fri, Jan 08, 2021 at 03:34:52PM +0100, Giulio Benetti wrote:
> Hi,
>
> On 1/8/21 10:23 AM, Maxime Ripard wrote:
> > Hi,
> >
> > Thanks for those patches
> >
> > On Thu, Jan 07, 2021 at 03:30:32AM +0100, Giulio Benetti wrote:
> > > From: Giulio Benetti
> > >
> > > It turned out(Maxime sugges
Hi,
On 1/8/21 10:23 AM, Maxime Ripard wrote:
Hi,
Thanks for those patches
On Thu, Jan 07, 2021 at 03:30:32AM +0100, Giulio Benetti wrote:
From: Giulio Benetti
It turned out(Maxime suggestion) that bit 26 of SUN4I_TCON0_IO_POL_REG is
dedicated to invert DCLK polarity and this makes thing rea
That patch only seem to undo what you did in patch 1
"
Already answered to Maxime
And another question (probably could be a stupid one):
in "/[PATCH v2 2/2] drm/sun4i: tcon: improve DCLK polarity handling/" I
see you deleted:
- clk_set_phase(tcon->dclk,
Hi,
Quote "
I'm not really sure why we need the first patch of this series here?
That patch only seem to undo what you did in patch 1
"
And another question (probably could be a stupid one):
in "/[PATCH v2 2/2] drm/sun4i: tcon: improve DCLK polarity handling/
Hi,
Thanks for those patches
On Thu, Jan 07, 2021 at 03:30:32AM +0100, Giulio Benetti wrote:
> From: Giulio Benetti
>
> It turned out(Maxime suggestion) that bit 26 of SUN4I_TCON0_IO_POL_REG is
> dedicated to invert DCLK polarity and this makes thing really easier than
> before. So let's handle
From: Giulio Benetti
It turned out(Maxime suggestion) that bit 26 of SUN4I_TCON0_IO_POL_REG is
dedicated to invert DCLK polarity and this makes thing really easier than
before. So let's handle DCLK polarity by adding
SUN4I_TCON0_IO_POL_DCLK_POSITIVE as bit 26 and activating according to
bus_flags
