On Wed, Jul 27, 2016 at 04:31:32PM +0800, Bibby Hsieh wrote:
> From: Junzhi Zhao
>
> Pixel clock should be 297MHz when resolution is 4K.
>
> Signed-off-by: Junzhi Zhao
> Signed-off-by: Bibby Hsieh
> ---
> drivers/gpu/drm/mediatek/mtk_dpi.c | 149
> +++-
> 1 f
Hi, Philipp,
Thanks for your comments.
On Wed, 2016-07-27 at 11:23 +0200, Philipp Zabel wrote:
> Am Mittwoch, den 27.07.2016, 16:31 +0800 schrieb Bibby Hsieh:
> > From: Junzhi Zhao
> >
> > Pixel clock should be 297MHz when resolution is 4K.
>
> This patch does two different things, please don'
From: Junzhi Zhao
Pixel clock should be 297MHz when resolution is 4K.
Signed-off-by: Junzhi Zhao
Signed-off-by: Bibby Hsieh
---
drivers/gpu/drm/mediatek/mtk_dpi.c | 149 +++-
1 file changed, 96 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/media
Am Mittwoch, den 27.07.2016, 16:31 +0800 schrieb Bibby Hsieh:
> From: Junzhi Zhao
>
> Pixel clock should be 297MHz when resolution is 4K.
This patch does two different things, please don't conflate them.
First, it adds support for 16*3 and 2*3 factors between PLL and pixel
clock. This should be
