On Thu, Feb 29, 2024 at 11:25:41AM +0100, Paweł Anikiel wrote:
> On Wed, Feb 28, 2024 at 7:10 PM Rob Herring wrote:
> >
> > On Wed, Feb 28, 2024 at 02:09:33PM +0100, Paweł Anikiel wrote:
> > > On Wed, Feb 28, 2024 at 1:18 PM Krzysztof Kozlowski
> > > wrote:
> > > >
> > > > On 28/02/2024 12:05, Pa
On Wed, Feb 28, 2024 at 7:10 PM Rob Herring wrote:
>
> On Wed, Feb 28, 2024 at 02:09:33PM +0100, Paweł Anikiel wrote:
> > On Wed, Feb 28, 2024 at 1:18 PM Krzysztof Kozlowski
> > wrote:
> > >
> > > On 28/02/2024 12:05, Paweł Anikiel wrote:
> > > > On Tue, Feb 27, 2024 at 3:29 PM Rob Herring wrote
On Wed, Feb 28, 2024 at 02:09:33PM +0100, Paweł Anikiel wrote:
> On Wed, Feb 28, 2024 at 1:18 PM Krzysztof Kozlowski
> wrote:
> >
> > On 28/02/2024 12:05, Paweł Anikiel wrote:
> > > On Tue, Feb 27, 2024 at 3:29 PM Rob Herring wrote:
> > >>
> > >> On Mon, Feb 26, 2024 at 11:59:42AM +0100, Paweł An
On Wed, Feb 28, 2024 at 1:18 PM Krzysztof Kozlowski
wrote:
>
> On 28/02/2024 12:05, Paweł Anikiel wrote:
> > On Tue, Feb 27, 2024 at 3:29 PM Rob Herring wrote:
> >>
> >> On Mon, Feb 26, 2024 at 11:59:42AM +0100, Paweł Anikiel wrote:
> >>> On Mon, Feb 26, 2024 at 10:13 AM Krzysztof Kozlowski
> >>>
On 28/02/2024 12:05, Paweł Anikiel wrote:
> On Tue, Feb 27, 2024 at 3:29 PM Rob Herring wrote:
>>
>> On Mon, Feb 26, 2024 at 11:59:42AM +0100, Paweł Anikiel wrote:
>>> On Mon, Feb 26, 2024 at 10:13 AM Krzysztof Kozlowski
>>> wrote:
On 21/02/2024 17:02, Paweł Anikiel wrote:
> The Int
On Tue, Feb 27, 2024 at 3:29 PM Rob Herring wrote:
>
> On Mon, Feb 26, 2024 at 11:59:42AM +0100, Paweł Anikiel wrote:
> > On Mon, Feb 26, 2024 at 10:13 AM Krzysztof Kozlowski
> > wrote:
> > >
> > > On 21/02/2024 17:02, Paweł Anikiel wrote:
> > > > The Intel Displayport RX IP is a part of the Disp
On Mon, Feb 26, 2024 at 11:59:42AM +0100, Paweł Anikiel wrote:
> On Mon, Feb 26, 2024 at 10:13 AM Krzysztof Kozlowski
> wrote:
> >
> > On 21/02/2024 17:02, Paweł Anikiel wrote:
> > > The Intel Displayport RX IP is a part of the DisplayPort Intel FPGA IP
> > > Core. It implements a DisplayPort 1.4
On Tue, Feb 27, 2024 at 02:11:27PM +0100, Paweł Anikiel wrote:
> On Mon, Feb 26, 2024 at 6:29 PM Krzysztof Kozlowski
> wrote:
> >
> > On 26/02/2024 13:43, Paweł Anikiel wrote:
> > > + intel,max-stream-count:
> > > +$ref: /schemas/types.yaml#/definitions/uint32
> > > +descripti
On Mon, Feb 26, 2024 at 6:29 PM Krzysztof Kozlowski
wrote:
>
> On 26/02/2024 13:43, Paweł Anikiel wrote:
> > + intel,max-stream-count:
> > +$ref: /schemas/types.yaml#/definitions/uint32
> > +description: Max stream count configuration parameter
> > +
> > + port:
> >>>
On 26/02/2024 13:43, Paweł Anikiel wrote:
> + intel,max-stream-count:
> +$ref: /schemas/types.yaml#/definitions/uint32
> +description: Max stream count configuration parameter
> +
> + port:
> +$ref: /schemas/graph.yaml#/properties/port
> +description: S
On Mon, Feb 26, 2024 at 1:06 PM Krzysztof Kozlowski
wrote:
>
> On 26/02/2024 11:59, Paweł Anikiel wrote:
> >>> +properties:
> >>> + compatible:
> >>> +const: intel,dprx-20.0.1
> >>> +
> >>> + reg:
> >>> +maxItems: 1
> >>> +
> >>> + interrupts:
> >>> +maxItems: 1
> >>> +
> >>> + int
On 26/02/2024 11:59, Paweł Anikiel wrote:
>>> +properties:
>>> + compatible:
>>> +const: intel,dprx-20.0.1
>>> +
>>> + reg:
>>> +maxItems: 1
>>> +
>>> + interrupts:
>>> +maxItems: 1
>>> +
>>> + intel,max-link-rate:
>>> +$ref: /schemas/types.yaml#/definitions/uint32
>>> +desc
On Mon, Feb 26, 2024 at 10:13 AM Krzysztof Kozlowski
wrote:
>
> On 21/02/2024 17:02, Paweł Anikiel wrote:
> > The Intel Displayport RX IP is a part of the DisplayPort Intel FPGA IP
> > Core. It implements a DisplayPort 1.4 receiver capable of HBR3 video
> > capture and Multi-Stream Transport. The
On 21/02/2024 17:02, Paweł Anikiel wrote:
> The Intel Displayport RX IP is a part of the DisplayPort Intel FPGA IP
> Core. It implements a DisplayPort 1.4 receiver capable of HBR3 video
> capture and Multi-Stream Transport. The user guide can be found here:
>
> https://www.intel.com/programmable/t
The Intel Displayport RX IP is a part of the DisplayPort Intel FPGA IP
Core. It implements a DisplayPort 1.4 receiver capable of HBR3 video
capture and Multi-Stream Transport. The user guide can be found here:
https://www.intel.com/programmable/technical-pdfs/683273.pdf
Signed-off-by: Paweł Aniki
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