[PATCH v3 03/19] clk: sunxi: Add PLL3 clock

2016-04-19 Thread Maxime Ripard
On Fri, Apr 15, 2016 at 03:34:41PM -0700, Stephen Boyd wrote: > On 03/23, Maxime Ripard wrote: > > The A10 SoCs and relatives have a PLL controller to drive the PLL3 and > > PLL7, clocked from a 3MHz oscillator, that drives the display related > > clocks (GPU, display engine, TCON, etc.) > > > > A

[PATCH v3 03/19] clk: sunxi: Add PLL3 clock

2016-04-15 Thread Stephen Boyd
On 03/23, Maxime Ripard wrote: > The A10 SoCs and relatives have a PLL controller to drive the PLL3 and > PLL7, clocked from a 3MHz oscillator, that drives the display related > clocks (GPU, display engine, TCON, etc.) > > Add a driver for it. > > Acked-by: Rob Herring > Acked-by: Chen-Yu Tsai

[PATCH v3 03/19] clk: sunxi: Add PLL3 clock

2016-03-23 Thread Maxime Ripard
The A10 SoCs and relatives have a PLL controller to drive the PLL3 and PLL7, clocked from a 3MHz oscillator, that drives the display related clocks (GPU, display engine, TCON, etc.) Add a driver for it. Acked-by: Rob Herring Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- Documentatio