On 04/04, Stefan Agner wrote:
> Similar to an earlier fix for the SAI clocks, the DCU clock hierarchy
> mixes the bus clock with the display controllers pixel clock. Tests
> have shown that the gates in CCM_CCGR3/9 registers do not control
> the DCU pixel clock, but only the register access clock (
On 2016-04-11 18:38, Shawn Guo wrote:
> On Mon, Apr 04, 2016 at 10:28:33PM -0700, Stefan Agner wrote:
>> Similar to an earlier fix for the SAI clocks, the DCU clock hierarchy
>> mixes the bus clock with the display controllers pixel clock. Tests
>> have shown that the gates in CCM_CCGR3/9 registers
On Mon, Apr 04, 2016 at 10:28:33PM -0700, Stefan Agner wrote:
> Similar to an earlier fix for the SAI clocks, the DCU clock hierarchy
> mixes the bus clock with the display controllers pixel clock. Tests
> have shown that the gates in CCM_CCGR3/9 registers do not control
> the DCU pixel clock, but
Similar to an earlier fix for the SAI clocks, the DCU clock hierarchy
mixes the bus clock with the display controllers pixel clock. Tests
have shown that the gates in CCM_CCGR3/9 registers do not control
the DCU pixel clock, but only the register access clock (bus clock).
Fix this by defining the