In order to prevent timeouts and stalls in the pipeline, the core clock
needs to be maxed at 500MHz during a modeset on the BCM2711.
Reviewed-by: Eric Anholt
Signed-off-by: Maxime Ripard
---
drivers/gpu/drm/vc4/vc4_drv.h | 2 ++
drivers/gpu/drm/vc4/vc4_hvs.c | 9 +
drivers/gpu/drm/vc4
Hi Maxime,
On 7/9/20 2:41 AM, Maxime Ripard wrote:
> In order to prevent timeouts and stalls in the pipeline, the core clock
> needs to be maxed at 500MHz during a modeset on the BCM2711.
>
> Reviewed-by: Eric Anholt
> Signed-off-by: Maxime Ripard
> ---
> drivers/gpu/drm/vc4/vc4_drv.h | 2 ++
On 9/1/20 8:21 PM, Chanwoo Choi wrote:
> Hi Maxime,
>
> On 7/9/20 2:41 AM, Maxime Ripard wrote:
>> In order to prevent timeouts and stalls in the pipeline, the core clock
>> needs to be maxed at 500MHz during a modeset on the BCM2711.
>>
>> Reviewed-by: Eric Anholt
>> Signed-off-by: Maxime Ripard
Hi,
On Tue, Sep 01, 2020 at 08:21:36PM +0900, Chanwoo Choi wrote:
> Hi Maxime,
>
> On 7/9/20 2:41 AM, Maxime Ripard wrote:
> > In order to prevent timeouts and stalls in the pipeline, the core clock
> > needs to be maxed at 500MHz during a modeset on the BCM2711.
> >
> > Reviewed-by: Eric Anholt