Re: [PATCHv2 0/3] Intel FPGA VIP Frame Buffer II DRM Driver

2017-05-11 Thread Daniel Vetter
On Thu, May 11, 2017 at 02:50:41AM +, Ong, Hean Loong wrote: > On Tue, 2017-05-09 at 09:40 -0700, Eric Anholt wrote: > > "Ong, Hean Loong" writes: > > > > > > > > On Mon, 2017-05-08 at 09:03 -0700, Eric Anholt wrote: > > > > > > > > "Ong, Hean Loong" writes: > > > > > > > > > > > > > >

Re: [PATCHv2 0/3] Intel FPGA VIP Frame Buffer II DRM Driver

2017-05-11 Thread Ong, Hean Loong
On Tue, 2017-05-09 at 09:40 -0700, Eric Anholt wrote: > "Ong, Hean Loong" writes: > > > > > On Mon, 2017-05-08 at 09:03 -0700, Eric Anholt wrote: > > > > > > "Ong, Hean Loong" writes: > > > > > > > > > > > > > > > On Thu, 2017-05-04 at 10:11 -0700, Eric Anholt wrote: > > > > > > > > > > >

Re: [PATCHv2 0/3] Intel FPGA VIP Frame Buffer II DRM Driver

2017-05-09 Thread Ong, Hean Loong
On Mon, 2017-05-08 at 09:03 -0700, Eric Anholt wrote: > "Ong, Hean Loong" writes: > > > > > On Thu, 2017-05-04 at 10:11 -0700, Eric Anholt wrote: > > > > > > "Ong, Hean Loong" writes: > > > > > > > > > > > > > > > On Wed, 2017-05-03 at 13:28 -0700, Eric Anholt wrote: > > > > > > > > > > >

Re: [PATCHv2 0/3] Intel FPGA VIP Frame Buffer II DRM Driver

2017-05-09 Thread Eric Anholt
"Ong, Hean Loong" writes: > On Mon, 2017-05-08 at 09:03 -0700, Eric Anholt wrote: >> "Ong, Hean Loong" writes: >> >> > >> > On Thu, 2017-05-04 at 10:11 -0700, Eric Anholt wrote: >> > > >> > > "Ong, Hean Loong" writes: >> > > >> > > > >> > > > >> > > > On Wed, 2017-05-03 at 13:28 -0700, Er

Re: [PATCHv2 0/3] Intel FPGA VIP Frame Buffer II DRM Driver

2017-05-08 Thread Ong, Hean Loong
On Thu, 2017-05-04 at 10:11 -0700, Eric Anholt wrote: > "Ong, Hean Loong" writes: > > > > > On Wed, 2017-05-03 at 13:28 -0700, Eric Anholt wrote: > > > > > > hean.loong@intel.com writes: > > > > > > > > > > > > > > > From: Ong Hean Loong > > > > > > > > Hi, > > > > > > > > The new Int

Re: [PATCHv2 0/3] Intel FPGA VIP Frame Buffer II DRM Driver

2017-05-08 Thread Eric Anholt
"Ong, Hean Loong" writes: > On Thu, 2017-05-04 at 10:11 -0700, Eric Anholt wrote: >> "Ong, Hean Loong" writes: >> >> > >> > On Wed, 2017-05-03 at 13:28 -0700, Eric Anholt wrote: >> > > >> > > hean.loong@intel.com writes: >> > > >> > > > >> > > > >> > > > From: Ong Hean Loong >> > > >

Re: [PATCHv2 0/3] Intel FPGA VIP Frame Buffer II DRM Driver

2017-05-04 Thread Ong, Hean Loong
On Wed, 2017-05-03 at 13:28 -0700, Eric Anholt wrote: > hean.loong@intel.com writes: > > > > > From: Ong Hean Loong > > > > Hi, > > > > The new Intel Arria10 SOC FPGA devkit has a Display Port IP > > component  > > which requires a new driver. This is a virtual driver in which the > > FGPA

Re: [PATCHv2 0/3] Intel FPGA VIP Frame Buffer II DRM Driver

2017-05-04 Thread Eric Anholt
"Ong, Hean Loong" writes: > On Wed, 2017-05-03 at 13:28 -0700, Eric Anholt wrote: >> hean.loong@intel.com writes: >> >> > >> > From: Ong Hean Loong >> > >> > Hi, >> > >> > The new Intel Arria10 SOC FPGA devkit has a Display Port IP >> > component  >> > which requires a new driver. This i

Re: [PATCHv2 0/3] Intel FPGA VIP Frame Buffer II DRM Driver

2017-05-04 Thread Daniel Vetter
On Wed, May 3, 2017 at 10:28 PM, Eric Anholt wrote: >> From: Ong Hean Loong >> >> Hi, >> >> The new Intel Arria10 SOC FPGA devkit has a Display Port IP component >> which requires a new driver. This is a virtual driver in which the >> FGPA hardware would enable the Display Port based on the infor

Re: [PATCHv2 0/3] Intel FPGA VIP Frame Buffer II DRM Driver

2017-05-03 Thread Eric Anholt
hean.loong@intel.com writes: > From: Ong Hean Loong > > Hi, > > The new Intel Arria10 SOC FPGA devkit has a Display Port IP component > which requires a new driver. This is a virtual driver in which the > FGPA hardware would enable the Display Port based on the information > and data provide

[PATCHv2 0/3] Intel FPGA VIP Frame Buffer II DRM Driver

2017-04-24 Thread hean . loong . ong
From: Ong Hean Loong Hi, The new Intel Arria10 SOC FPGA devkit has a Display Port IP component which requires a new driver. This is a virtual driver in which the FGPA hardware would enable the Display Port based on the information and data provided from the DRM frame buffer from the OS. Basical