Hi Ilia,
Thanks for your answer.
On 16-06-2016 13:39, Ilia Mirkin wrote:
> On Thu, Jun 16, 2016 at 8:09 AM, Jose Abreu
> wrote:
>> Hi Daniel,
>>
>> Sorry to bother you again. I promise this is the last time :)
>>
>> On 15-06-2016 11:15, Daniel Vetter wrote:
>>> On Wed, Jun 15, 2016 at 11:48
On Thu, Jun 16, 2016 at 01:09:34PM +0100, Jose Abreu wrote:
> Hi Daniel,
>
> Sorry to bother you again. I promise this is the last time :)
>
> On 15-06-2016 11:15, Daniel Vetter wrote:
> > On Wed, Jun 15, 2016 at 11:48 AM, Jose Abreu
> > wrote:
> >> On 15-06-2016 09:52, Daniel Vetter wrote:
>
Hi Daniel,
Sorry to bother you again. I promise this is the last time :)
On 15-06-2016 11:15, Daniel Vetter wrote:
> On Wed, Jun 15, 2016 at 11:48 AM, Jose Abreu
> wrote:
>> On 15-06-2016 09:52, Daniel Vetter wrote:
>>> On Tue, Jun 14, 2016 at 1:19 PM, Jose Abreu
>>> wrote:
> I assume
On Thu, Jun 16, 2016 at 8:09 AM, Jose Abreu wrote:
> Hi Daniel,
>
> Sorry to bother you again. I promise this is the last time :)
>
> On 15-06-2016 11:15, Daniel Vetter wrote:
>> On Wed, Jun 15, 2016 at 11:48 AM, Jose Abreu
>> wrote:
>>> On 15-06-2016 09:52, Daniel Vetter wrote:
On Tue,
On Wed, Jun 15, 2016 at 11:48 AM, Jose Abreu wrote:
>
> On 15-06-2016 09:52, Daniel Vetter wrote:
>> On Tue, Jun 14, 2016 at 1:19 PM, Jose Abreu
>> wrote:
I assume that xilinx VDMA is the only way to feed pixel data into your
display pipeline. Under that assumption:
On Tue, Jun 14, 2016 at 1:19 PM, Jose Abreu wrote:
>> I assume that xilinx VDMA is the only way to feed pixel data into your
>> display pipeline. Under that assumption:
>>
>> drm_plane should map to Xilinx VDMA, and the drm_plane->drm_crtc link
>> would represent the dma channel. With atomic you
Hi Daniel,
On 15-06-2016 09:52, Daniel Vetter wrote:
> On Tue, Jun 14, 2016 at 1:19 PM, Jose Abreu
> wrote:
>>> I assume that xilinx VDMA is the only way to feed pixel data into your
>>> display pipeline. Under that assumption:
>>>
>>> drm_plane should map to Xilinx VDMA, and the
t;>> On 26-05-2016 09:06, Daniel Vetter wrote:
>>>> On Wed, May 25, 2016 at 04:46:15PM +0100, Jose Abreu wrote:
>>>>> Hi all,
>>>>>
>>>>> Currently I am trying to develop a DRM driver that will use
>>>>> Xilinx VDMA to tran
at 04:46:15PM +0100, Jose Abreu wrote:
> >>> Hi all,
> >>>
> >>> Currently I am trying to develop a DRM driver that will use
> >>> Xilinx VDMA to transfer video data to a HDMI TX Phy and I am
> >>> facing a difficulty regarding the under
velop a DRM driver that will use
>>> Xilinx VDMA to transfer video data to a HDMI TX Phy and I am
>>> facing a difficulty regarding the understanding of the DRM DMA
>>> Engine. I looked at several sources and at the DRM core source
>>> but the flow of creating and
I TX Phy and I am
>> facing a difficulty regarding the understanding of the DRM DMA
>> Engine. I looked at several sources and at the DRM core source
>> but the flow of creating and interfacing with the DMA controller
>> is still not clear to me.
>>
>> At DRI web p
On Wed, May 25, 2016 at 04:46:15PM +0100, Jose Abreu wrote:
> Hi all,
>
> Currently I am trying to develop a DRM driver that will use
> Xilinx VDMA to transfer video data to a HDMI TX Phy and I am
> facing a difficulty regarding the understanding of the DRM DMA
> Engine. I
Hi all,
Currently I am trying to develop a DRM driver that will use
Xilinx VDMA to transfer video data to a HDMI TX Phy and I am
facing a difficulty regarding the understanding of the DRM DMA
Engine. I looked at several sources and at the DRM core source
but the flow of creating and interfacing
Hi all,
Currently I am trying to develop a DRM driver that will use
Xilinx VDMA to transfer video data to a HDMI TX Phy and I am
facing a difficulty regarding the understanding of the DRM DMA
Engine. I looked at several sources and at the DRM core source
but the flow of creating and interfacing
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