nel.org; 'Jernej Skrabec' ;
> 'Laurent Pinchart' ; 'Andrzej Hajda'
> ; 'Marek Szyprowski' ;
> ker...@pengutronix.de; 'Jagan Teki'
> Subject: Re: [PATCH 3/5] drm/bridge: samsung-dsim: update PLL reference
> clock
>
> On Tue, 05 Sep 2023 18:06:06 +0900, 대인기/Tizen Platform Lab(
ert Foss
> > ; Jonas Karlman ; dri-
> > de...@lists.freedesktop.org; linux-ker...@vger.kernel.org; Jernej Skrabec
> > ; Laurent Pinchart
> > ; Andrzej Hajda
> > ; Marek Szyprowski ;
> > ker...@pengutronix.de; Jagan Teki
> > Subject: Re: [PATCH 3/5] drm/bri
bec
> ; Laurent Pinchart
> ; Andrzej Hajda
> ; Marek Szyprowski ;
> ker...@pengutronix.de; Jagan Teki
> Subject: Re: [PATCH 3/5] drm/bridge: samsung-dsim: update PLL reference
> clock
>
> On Mon, 04 Sep 2023 14:44:41 +0900, Inki Dae wrote:
> > 2023년 8월 29일 (화) 오
On Mon, 04 Sep 2023 14:44:41 +0900, Inki Dae wrote:
> 2023년 8월 29일 (화) 오전 12:59, Michael Tretter 님이 작성:
> >
> > The PLL requires a clock between 2 MHz and 30 MHz after the pre-divider.
> > The reference clock for the PLL may change due to changes to it's parent
> > clock. Thus, the frequency may
2023년 8월 29일 (화) 오전 12:59, Michael Tretter 님이 작성:
>
> The PLL requires a clock between 2 MHz and 30 MHz after the pre-divider.
> The reference clock for the PLL may change due to changes to it's parent
> clock. Thus, the frequency may be out of range or unsuited for
> generating the high speed
On Mon, 28 Aug 2023 13:17:44 -0500, Adam Ford wrote:
> On Mon, Aug 28, 2023 at 11:42 AM Marco Felsch wrote:
> >
> > On 23-08-28, Michael Tretter wrote:
> > > The PLL requires a clock between 2 MHz and 30 MHz after the pre-divider.
> > > The reference clock for the PLL may change due to changes to
On Mon, Aug 28, 2023 at 11:42 AM Marco Felsch wrote:
>
> On 23-08-28, Michael Tretter wrote:
> > The PLL requires a clock between 2 MHz and 30 MHz after the pre-divider.
> > The reference clock for the PLL may change due to changes to it's parent
> > clock. Thus, the frequency may be out of range
On 23-08-28, Michael Tretter wrote:
> The PLL requires a clock between 2 MHz and 30 MHz after the pre-divider.
> The reference clock for the PLL may change due to changes to it's parent
> clock. Thus, the frequency may be out of range or unsuited for
> generating the high speed clock for MIPI DSI.
