On 2023-10-27 12:41, Boris Brezillon wrote:
> On Fri, 27 Oct 2023 10:32:52 -0400
> Luben Tuikov wrote:
>
>> On 2023-10-27 04:25, Boris Brezillon wrote:
>>> Hi Danilo,
>>>
>>> On Thu, 26 Oct 2023 18:13:00 +0200
>>> Danilo Krummrich wrote:
>>>
Currently, job flow control is implemented
On 2023-10-27 12:31, Boris Brezillon wrote:
> On Fri, 27 Oct 2023 16:23:24 +0200
> Danilo Krummrich wrote:
>
>> On 10/27/23 10:25, Boris Brezillon wrote:
>>> Hi Danilo,
>>>
>>> On Thu, 26 Oct 2023 18:13:00 +0200
>>> Danilo Krummrich wrote:
>>>
Currently, job flow control is implemented
Hi,
On 2023-10-27 12:26, Boris Brezillon wrote:
> On Fri, 27 Oct 2023 16:34:26 +0200
> Danilo Krummrich wrote:
>
>> On 10/27/23 09:17, Boris Brezillon wrote:
>>> Hi Danilo,
>>>
>>> On Thu, 26 Oct 2023 18:13:00 +0200
>>> Danilo Krummrich wrote:
>>>
+
+ /**
+ *
This panel is found on laptops e.g., variants of the Thinkpad X13s.
Configuration was collected from the panel's EDID.
Signed-off-by: Clayton Craft
---
drivers/gpu/drm/panel/panel-edp.c | 27 +++
1 file changed, 27 insertions(+)
diff --git
On Fri, 27 Oct 2023 at 22:45, Rob Clark wrote:
>
> From: Rob Clark
>
> The EXT_external_objects extension is a bit awkward as it doesn't pass
> explicit modifiers, leaving the importer to guess with incomplete
> information. In the case of vk (turnip) exporting and gl (freedreno)
> importing,
On Fri, 27 Oct 2023 at 19:59, Rob Clark wrote:
>
> From: Rob Clark
>
> We shouldn't be running the job in error cases. This also avoids having
> to think too hard about where the objs get unpinned (and if necessary,
> the resv takes over tracking that the obj is busy).. ie. error cases it
>
Hello,
On Fri, Oct 27, 2023 at 11:57:45AM -0400, Hamza Mahfooz wrote:
> On 10/27/23 11:55, Lakha, Bhawanpreet wrote:
> > [AMD Official Use Only - General]
> >
> >
> >
> > There was a consensus to use memset instead of {0}. I remember making
> > changes related to that previously.
>
> Hm, seems
On Fri, 27 Oct 2023 at 19:59, Rob Clark wrote:
>
> From: Rob Clark
>
> The only point it is called is before pinning objects, so the "unpin"
> part of the name is fiction. Just remove call submit_cleanup_bo()
Nit: 'remove it and call'
Other than that:
Reviewed-by: Dmitry Baryshkov
>
On Sat, 28 Oct 2023 at 00:02, Abhinav Kumar wrote:
>
>
>
> On 10/25/2023 2:23 AM, Dmitry Baryshkov wrote:
> > From: Abel Vesa
> >
> > In case of the eDP connection there is no subconnetor and as such no
> > subconnector property. Put drm_dp_set_subconnector_property() calls
> > under the !is_edp
Reported by coccinelle, the following patch will move the
following 1 element arrays to flexible arrays.
drivers/gpu/drm/radeon/atombios.h:5523:32-48: WARNING use flexible-array member
instead
(https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arrays)
On 10/20/2023 8:02 AM, Chris Morgan wrote:
On Thu, Oct 19, 2023 at 10:22:24AM -0700, Jessica Zhang wrote:
On 10/18/2023 9:18 AM, Chris Morgan wrote:
From: Chris Morgan
Refactor the driver to add support for the powkiddy,rk2023-panel
panel. This panel is extremely similar to the
Drop DPU_PLANE_COLOR_FILL_FLAG and check the DRM solid_fill property to
determine if the plane is solid fill. In addition drop the DPU plane
color_fill field as we can now use drm_plane_state.solid_fill instead,
and pass in drm_plane_state.alpha to _dpu_plane_color_fill_pipe() to
allow userspace
Add support for pixel_source property to drm_plane and related
documentation. In addition, force pixel_source to
DRM_PLANE_PIXEL_SOURCE_FB in DRM_IOCTL_MODE_SETPLANE as to not break
legacy userspace.
This enum property will allow user to specify a pixel source for the
plane. Possible pixel
Currently framebuffer checks happen directly in
drm_atomic_plane_check(). Move these checks into their own helper
method.
Reviewed-by: Dmitry Baryshkov
Acked-by: Harry Wentland
Acked-by: Sebastian Wick
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic.c | 130
Some drivers support hardware that have optimizations for solid fill
planes. This series aims to expose these capabilities to userspace as
some compositors have a solid fill flag (ex. SOLID_COLOR in the Android
hardware composer HAL) that can be set by apps like the Android Gears
test app.
In
Add solid_fill property data to the atomic plane state dump.
Reviewed-by: Dmitry Baryshkov
Acked-by: Harry Wentland
Acked-by: Sebastian Wick
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic.c | 4
drivers/gpu/drm/drm_plane.c | 8
include/drm/drm_plane.h | 3 +++
Loosen the requirements for atomic and legacy commit so that, in cases
where pixel_source != FB, the commit can still go through.
This includes adding framebuffer NULL checks in other areas to account for
FB being NULL when non-FB pixel sources are enabled.
To disable a plane, the pixel_source
Add solid_fill and pixel_source properties to DPU plane
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
Add "SOLID_FILL" as a valid pixel source. If the pixel_source property is
set to "SOLID_FILL", it will display data from the drm_plane "solid_fill"
blob property.
Reviewed-by: Dmitry Baryshkov
Acked-by: Pekka Paalanen
Acked-by: Harry Wentland
Acked-by: Sebastian Wick
Signed-off-by: Jessica
Add pixel source to the atomic plane state dump
Reviewed-by: Dmitry Baryshkov
Acked-by: Harry Wentland
Acked-by: Sebastian Wick
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/drm_atomic.c| 1 +
drivers/gpu/drm/drm_blend.c | 1 +
drivers/gpu/drm/drm_crtc_internal.h | 1 +
3
Since solid fill planes allow for a NULL framebuffer in a valid commit,
add NULL framebuffer checks to atomic commit calls within DPU.
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 9 +++-
Document and add support for solid_fill property to drm_plane. In
addition, add support for setting and getting the values for solid_fill.
To enable solid fill planes, userspace must assign a property blob to
the "solid_fill" plane property containing the following information:
struct
From: John Harrison
These w/a's can have signficant performance implications for any
workload which uses both RCS and CCS. On the other hand, the hang
itself is only seen in one or two very specific workloads. So add a
module parameter to control whether the w/a's are enabled or not and
default
From: John Harrison
Use the new w/a KLV support to enable a MTL w/a. Note, this w/a is a
super-set of Wa_16019325821, so requires turning that one as well as
setting the new flag for Wa_14019159160 itself.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 3 ++
From: John Harrison
Some platforms require holding RCS context switches until CCS is idle
(the reverse w/a of Wa_14014475959). Some platforms require both
versions.
Signed-off-by: John Harrison
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 19 +++
From: John Harrison
To prevent running out of bits, new w/a enable flags are being added
via a KLV system instead of a 32 bit flags word.
Signed-off-by: John Harrison
---
.../gpu/drm/i915/gt/uc/abi/guc_errors_abi.h | 1 +
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 +
From: John Harrison
Enable Wa_14019159160 and Wa_16019325821 for MTL
RCS/CCS workarounds for MTL.
v2: Fix bug in WA KLV implementation (offset not being reset to start
of list). Add better comment to prep patch about how KLVs can be added.
Add a module parameter override and disable the w/a
On 10/6/2023 17:38, Belgaumkar, Vinay wrote:
On 9/15/2023 2:55 PM, john.c.harri...@intel.com wrote:
From: John Harrison
To prevent running out of bits, new w/a enable flags are being added
via a KLV system instead of a 32 bit flags word.
Signed-off-by: John Harrison
---
On 10/6/2023 17:10, Belgaumkar, Vinay wrote:
On 9/15/2023 2:55 PM, john.c.harri...@intel.com wrote:
From: John Harrison
Some platforms require holding RCS context switches until CCS is idle
(the reverse w/a of Wa_14014475959). Some platforms require both
versions.
Signed-off-by: John
On 10/25/2023 2:23 AM, Dmitry Baryshkov wrote:
From: Abel Vesa
In case of the eDP connection there is no subconnetor and as such no
subconnector property. Put drm_dp_set_subconnector_property() calls
under the !is_edp condition.
Fixes: bfcc3d8f94f4 ("drm/msm/dp: support setting the DP
Javier Martinez Canillas writes:
[...]
>>> Pushed to drm-misc (drm-misc-next). Thanks!
>>
>> Given what introduced this is before the drm-misc-next-2023-10-19 tag,
>> isn't it going into 6.7 and needs to be in the fixes branch? Though that
>> doesn't exist yet for 6.7 fixes. I don't
Rob Herring writes:
Hello Rob,
> On Fri, Oct 27, 2023 at 11:30:56AM +0200, Javier Martinez Canillas wrote:
>> Rob Herring writes:
>>
>> > On Sat, 21 Oct 2023 00:30:17 +0200, Javier Martinez Canillas wrote:
>> >> This is a leftover from when the binding schema had the compatible string
>> >>
Hi Dave, Sima,
Fixes for 6.7.
The following changes since commit 5258dfd4a6adb5f45f046b0dd2e73c680f880d9d:
usb: typec: altmodes/displayport: fixup drm internal api change vs new user.
(2023-10-27 07:55:41 +1000)
are available in the Git repository at:
From: Rob Clark
The EXT_external_objects extension is a bit awkward as it doesn't pass
explicit modifiers, leaving the importer to guess with incomplete
information. In the case of vk (turnip) exporting and gl (freedreno)
importing, the "OPTIMAL_TILING_EXT" layout depends on VkImageCreateInfo
From: Carl Vanderlip
Current wrapper is right-sized to the message being transferred;
however, this is smaller than the structure defining message wrappers
since the trailing element is a union of message/transfer headers of
various sizes (8 and 32 bytes on 32-bit system where issue was
[Public]
> -Original Message-
> From: José Pekkarinen
> Sent: Friday, October 27, 2023 12:59 PM
> To: Deucher, Alexander ; Koenig, Christian
> ; Pan, Xinhui ;
> sk...@linuxfoundation.org
> Cc: José Pekkarinen ; airl...@gmail.com;
> dan...@ffwll.ch; amd-...@lists.freedesktop.org; dri-
>
On 27/10/2023 18:28, Harshit Mogalapalli wrote:
When i915 perf interface is not available dereferencing it will lead to
NULL dereferences.
As returning -ENOTSUPP is pretty clear return when perf interface is not
available.
Fixes: 2fec539112e8 ("i915/perf: Replace DRM_DEBUG with driver
On 26/10/2023 12:31, Maxime Ripard wrote:
Hi,
On Thu, Oct 26, 2023 at 11:27:18AM -0300, Helen Koike wrote:
On 26/10/2023 10:27, Maxime Ripard wrote:
On Thu, Oct 26, 2023 at 09:08:03AM -0300, Helen Koike wrote:
On 26/10/2023 09:01, Helen Koike wrote:
On 26/10/2023 07:58, Maxime Ripard
When i915 perf interface is not available dereferencing it will lead to
NULL dereferences.
As returning -ENOTSUPP is pretty clear return when perf interface is not
available.
Fixes: 2fec539112e8 ("i915/perf: Replace DRM_DEBUG with driver specific drm_dbg
call")
Suggested-by: Tvrtko Ursulin
On Fri, Oct 27, 2023 at 11:30:56AM +0200, Javier Martinez Canillas wrote:
> Rob Herring writes:
>
> > On Sat, 21 Oct 2023 00:30:17 +0200, Javier Martinez Canillas wrote:
> >> This is a leftover from when the binding schema had the compatible string
> >> property enum as a 'oneOf' child and the
Hi Tvrtko,
On 27/10/23 8:17 pm, Tvrtko Ursulin wrote:
On 27/10/2023 15:11, Andrzej Hajda wrote:
On 27.10.2023 16:07, Harshit Mogalapalli wrote:
When i915 perf interface is not available dereferencing it will lead to
NULL dereferences.
Fix this by using DRM_DEBUG() which the scenario before
From: Rob Clark
In cases where the # is known ahead of time, it is silly to do the table
resize dance.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 4 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 ++--
From: Rob Clark
Replace the ww_mutex locking dance with the drm_exec helper.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/Kconfig | 1 +
drivers/gpu/drm/msm/msm_gem.h| 5 +-
drivers/gpu/drm/msm/msm_gem_submit.c | 117 +--
3 files changed, 24
From: Rob Clark
Now that it only handles unlock duty, drop the superfluous arg and
rename it.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem_submit.c | 15 +--
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gem_submit.c
From: Rob Clark
Untangle unpinning from unlock/unref loop. The unpin only happens in
error paths so it is easier to decouple from the normal unlock path.
Since we never have an intermediate state where a subset of buffers
are pinned (ie. we never bail out of the pin or unpin loops) we can
From: Rob Clark
We shouldn't be running the job in error cases. This also avoids having
to think too hard about where the objs get unpinned (and if necessary,
the resv takes over tracking that the obj is busy).. ie. error cases it
always happens synchronously, and normal cases it happens from
From: Rob Clark
The only point it is called is before pinning objects, so the "unpin"
part of the name is fiction. Just remove call submit_cleanup_bo()
directly.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem_submit.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
From: Rob Clark
This was a small optimization for pre-soft-pin userspace. But mesa
switched to soft-pin nearly 5yrs ago. So lets drop the optimization
and simplify the code.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.h| 2 --
drivers/gpu/drm/msm/msm_gem_submit.c | 44
From: Rob Clark
Simplify the exec path (removing a legacy optimization) and convert to
drm_exec. One drm_exec patch to allow passing in the expected # of GEM
objects to avoid re-allocation.
I'd be a bit happier if I could avoid the extra objects table allocation
in drm_exec in the first place,
Hi,
On Thu, Oct 26, 2023 at 8:05 PM Sheng-Liang Pan
wrote:
>
> Add panel identification entry for
> - AUO B116XTN02 family (product ID:0x235c)
> - BOE NT116WHM-N21,836X2 (product ID:0x09c3)
> - BOE NV116WHM-N49 V8.0 (product ID:0x0979)
>
> Signed-off-by: Sheng-Liang Pan
>
> ---
>
>
From: Pranjal Ramajor Asha Kanojiya
Add support to partially execute a slice which is resized to zero.
Executing a zero size slice in a BO should mean that there is no DMA
transfers involved but you should still configure doorbell and semaphores.
For example consider a BO of size 18K and it is
On Fri, 27 Oct 2023 10:32:52 -0400
Luben Tuikov wrote:
> On 2023-10-27 04:25, Boris Brezillon wrote:
> > Hi Danilo,
> >
> > On Thu, 26 Oct 2023 18:13:00 +0200
> > Danilo Krummrich wrote:
> >
> >> Currently, job flow control is implemented simply by limiting the number
> >> of jobs in
On Fri, Oct 27, 2023 at 06:48:44PM +0300, Ville Syrjälä wrote:
> On Tue, Oct 24, 2023 at 01:22:17PM +0300, Imre Deak wrote:
> > Add helpers drivers can use to calculate the BW allocation overhead -
> > due to SSC, FEC, DSC and data alignment on symbol cycles - and the
> > channel coding efficiency
Sequential DMA bursts improve NIC/RAM usage thanks to the basic NIC
hardware optimizations available when performing in-order sequential
accesses. This can be further enforced with the IPU DMA locking
mechanism which basically prevents any other IP to access the
interconnect for a longer time
On Fri, 27 Oct 2023 16:23:24 +0200
Danilo Krummrich wrote:
> On 10/27/23 10:25, Boris Brezillon wrote:
> > Hi Danilo,
> >
> > On Thu, 26 Oct 2023 18:13:00 +0200
> > Danilo Krummrich wrote:
> >
> >> Currently, job flow control is implemented simply by limiting the number
> >> of jobs in
On Fri, 27 Oct 2023 16:34:26 +0200
Danilo Krummrich wrote:
> On 10/27/23 09:17, Boris Brezillon wrote:
> > Hi Danilo,
> >
> > On Thu, 26 Oct 2023 18:13:00 +0200
> > Danilo Krummrich wrote:
> >
> >> +
> >> + /**
> >> + * @update_job_credits: Called once the scheduler is considering this
>
On 10/16/2023 11:01 AM, Jeffrey Hugo wrote:
AIC100 supports a timesync mechanism that allows AIC100 to timestamp
device logs with a host based time. This becomes useful for putting host
logs in a unified timeline with device logs for debugging and performance
profiling. The mechanism consists of
On 10/27/23 11:55, Lakha, Bhawanpreet wrote:
[AMD Official Use Only - General]
There was a consensus to use memset instead of {0}. I remember making
changes related to that previously.
Hm, seems like it's used rather consistently in the DM and in DC
though.
Bhawan
On 10/22/2023 5:06 AM, Stanislaw Gruszka wrote:
On Mon, Oct 16, 2023 at 11:01:13AM -0600, Jeffrey Hugo wrote:
From: Ajit Pal Singh
Device and Host have a time synchronization mechanism that happens once
during boot when device is in SBL mode. After that, in mission-mode there
is no timesync.
[AMD Official Use Only - General]
There was a consensus to use memset instead of {0}. I remember making changes
related to that previously.
Bhawan
From: Mahfooz, Hamza
Sent: October 27, 2023 11:53 AM
To: Yuran Pereira ; airl...@gmail.com
Cc: Li, Sun peng
Also, please write the tagline in present tense.
On 10/27/23 11:53, Hamza Mahfooz wrote:
On 10/26/23 17:25, Yuran Pereira wrote:
Since `pr_config` is not initialized after its declaration, the
following operations with `replay_enable_option` may be performed
when `replay_enable_option` is
On 10/26/23 17:25, Yuran Pereira wrote:
Since `pr_config` is not initialized after its declaration, the
following operations with `replay_enable_option` may be performed
when `replay_enable_option` is holding junk values which could
possibly lead to undefined behaviour
```
...
[AMD Official Use Only - General]
Thanks,
Reviewed-by: Bhawanpreet Lakha
From: Yuran Pereira
Sent: October 26, 2023 5:25 PM
To: airl...@gmail.com
Cc: Yuran Pereira ; Wentland, Harry
; Li, Sun peng (Leo) ; Siqueira,
Rodrigo ; Deucher, Alexander
; Koenig,
On Tue, Oct 24, 2023 at 01:22:17PM +0300, Imre Deak wrote:
> Add helpers drivers can use to calculate the BW allocation overhead -
> due to SSC, FEC, DSC and data alignment on symbol cycles - and the
> channel coding efficiency - due to the 8b/10b, 128b/132b encoding. On
> 128b/132b links the FEC
The endianness of the target is currently determined based on
preprocessor symbols. Unfortunately some symbols checked are wrong
(sparc64-linux-gnu-gcc does not define __BIG_ENDIAN__ or SPARC), and
several checks for big-endian architectures are missing.
Fix this by introducing a new
Signed-off-by: Geert Uytterhoeven
---
v4:
- No changes,
v3:
- Update for suffix change from "be" to "_BE", cfr. commit
ffb9375a505700ad ("xf86drm: handle DRM_FORMAT_BIG_ENDIAN in
drmGetFormatName()"),
v2:
- New.
---
tests/util/format.c | 3 +++
1 file changed, 3 insertions(+)
Hi all,
This patch series fixes some endianness issues in libdrm.
It has been tested on ARAnyM using a work-in-progress Atari DRM driver.
After this, the smpte and tiles modetest patterns and the pwetty markers
are rendered correctly using the XR24, RG16, and RG16BE formats on
big-endian
DRM formats are defined to be little-endian, unless the
DRM_FORMAT_BIG_ENDIAN flag is set. Hence writes of multi-byte pixel
values need to take endianness into account.
Introduce a swap16() helper to byteswap 16-bit values, and a
cpu_to_le16() helper to convert 16-bit values from CPU-endian to
Add support for rendering the crosshairs in a buffer using the
big-endian RGB565 format.
Signed-off-by: Geert Uytterhoeven
---
v4:
- No changes,
v3:
- No changes,
v2:
- New.
---
tests/util/pattern.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/util/pattern.c
Cairo always uses native byte order for rendering.
Hence if the byte order of the frame buffer differs from the byte order
of the CPU, the frame buffer contents need to be byteswapped twice: once
before rendering, to convert to native byte order, and a second time
after rendering, to restore the
Add support for creating buffers using big-endian formats.
For now this is limited to XRGB1555 and RGB565, which are the most
common big-endian formats.
Signed-off-by: Geert Uytterhoeven
---
v4:
- No changes,
v3:
- No changes,
v2:
- New.
---
tests/modetest/buffers.c | 4
1 file
When specifying a frame buffer format like "RG16_BE" (big-endian RG16),
modetest still uses the little-endian variant, as the format string is
truncated to four characters.
Fix this by increasing the format string size to 8 bytes (7 characters +
NUL terminator).
Signed-off-by: Geert Uytterhoeven
DRM formats are defined to be little-endian, unless the
DRM_FORMAT_BIG_ENDIAN flag is set. Hence writes of multi-byte pixel
values need to take endianness into account.
Introduce a swap32() helper to byteswap 32-bit values, and a
cpu_to_le32() helper to convert 32-bit values from CPU-endian to
Add support for drawing the SMPTE and tiles test patterns in buffers
using big-endian formats.
For now this is limited to XRGB1555 and RGB565, which are the most
common big-endian formats.
Signed-off-by: Geert Uytterhoeven
---
v4:
- No changes,
v3:
- Increase indentation after definition
On 10/16/2023 11:00 AM, Jeffrey Hugo wrote:
From: Carl Vanderlip
Several virtualization use-cases either don't support 32 MultiMSIs
(Xen/VMware) or have significant drawbacks to their use (KVM's vIOMMU,
which is required to support 32 MSI, needs to allocate an alternate
system memory space for
From: Arnd Bergmann
The usage count of struct dev_pm_info is an implementation detail that
is only available if CONFIG_PM is enabled, so printing it in a debug message
causes a build failure in configurations without PM:
In file included from include/linux/device.h:15,
from
On 10/25/2023 3:43 AM, Stanislaw Gruszka wrote:
From: Andrzej Kacprowski
The VPU needs non zero time to enter IDLE state after responding to
D0i3 entry message. If the driver does not wait for the VPU to enter
IDLE state it could cause warm boot failures.
Signed-off-by: Andrzej Kacprowski
On 10/25/2023 3:43 AM, Stanislaw Gruszka wrote:
From: Andrzej Kacprowski
Currently the VPU firmware prepares for D0i3 every time the VPU
is entering D0i2 Idle state. This is not optimal as we might not
enter D0i3 every time we enter D0i2 Idle and this preparation
is quite costly.
This
On 10/27/23 16:59, Luben Tuikov wrote:
Hi Danilo,
On 2023-10-27 10:45, Danilo Krummrich wrote:
Hi Luben,
On 10/26/23 23:13, Luben Tuikov wrote:
On 2023-10-26 12:13, Danilo Krummrich wrote:
Currently, job flow control is implemented simply by limiting the number
of jobs in flight. Therefore,
On 10/25/2023 3:43 AM, Stanislaw Gruszka wrote:
From: Andrzej Kacprowski
The driver needs to capture the D0i3 entry timestamp to
calculate D0i3 residency time.
The D0i3 residency time and the VPU timestamp are passed
to the firmware at D0i3 exit (warm boot).
Signed-off-by: Andrzej Kacprowski
Hi Danilo,
On 2023-10-27 10:45, Danilo Krummrich wrote:
> Hi Luben,
>
> On 10/26/23 23:13, Luben Tuikov wrote:
>> On 2023-10-26 12:13, Danilo Krummrich wrote:
>>> Currently, job flow control is implemented simply by limiting the number
>>> of jobs in flight. Therefore, a scheduler is initialized
On 10/25/2023 3:43 AM, Stanislaw Gruszka wrote:
From: Andrzej Kacprowski
The firmware needs to know the time spend in D0i3/D3 to
spent?
calculate telemetry data. The D0i3/D3 residency time is
calculated by the driver and passed to the firmware
in the boot parameters.
The driver also
On 10/25/2023 3:43 AM, Stanislaw Gruszka wrote:
From: Karol Wachowski
Split ivpu_ipc_send_receive() implementation to have a version
that does not call pm_runtime_resume_and_get(). That implementation
can be invoked when device is up and runtime resume is prohibited
(for example at the end of
On 27/10/2023 15:11, Andrzej Hajda wrote:
On 27.10.2023 16:07, Harshit Mogalapalli wrote:
When i915 perf interface is not available dereferencing it will lead to
NULL dereferences.
Fix this by using DRM_DEBUG() which the scenario before the commit in
the Fixes tag.
Fixes: 2fec539112e8
On 10/25/2023 3:43 AM, Stanislaw Gruszka wrote:
From: Karol Wachowski
Change meaning of test_mode module parameter from integer value
to bitmask allowing setting different test features with corresponding
bits.
Signed-off-by: Karol Wachowski
Reviewed-by: Stanislaw Gruszka
Signed-off-by:
On 10/27/23 03:03, Luben Tuikov wrote:
On 2023-10-26 17:13, Luben Tuikov wrote:
On 2023-10-26 12:13, Danilo Krummrich wrote:
Currently, job flow control is implemented simply by limiting the number
of jobs in flight. Therefore, a scheduler is initialized with a credit
limit that corresponds to
Hi Luben,
On 10/26/23 23:13, Luben Tuikov wrote:
On 2023-10-26 12:13, Danilo Krummrich wrote:
Currently, job flow control is implemented simply by limiting the number
of jobs in flight. Therefore, a scheduler is initialized with a credit
limit that corresponds to the number of jobs which can
On 10/25/2023 3:43 AM, Stanislaw Gruszka wrote:
From: Andrzej Kacprowski
Add test_mode = 3 that add VPU_JOB_FLAGS_NULL_SUBMISSION_MASK
flag to the job send to the VPU device. Then the VPU will process
the job but won't execute commands (except the command to signal
the fence).
This can b used
On 10/25/2023 3:43 AM, Stanislaw Gruszka wrote:
From: Karol Wachowski
Setting a non-zero work point resets the IP hence IP_RESET
trigger is redundant.
Signed-off-by: Karol Wachowski
Reviewed-by: Stanislaw Gruszka
Signed-off-by: Stanislaw Gruszka
Reviewed-by: Jeffrey Hugo
On 10/25/2023 3:43 AM, Stanislaw Gruszka wrote:
From: Tomasz Rusinowicz
Add new debugfs file to set dvfs_mode FW boot parameter and restart
the FW to allow experimenting with DVFS (dynamic voltage & frequency
scaling).
Signed-off-by: Tomasz Rusinowicz
Signed-off-by: Stanislaw Gruszka
$SUBJECT has a spelling error of "declaration"
On 10/25/2023 3:43 AM, Stanislaw Gruszka wrote:
Cleanup drm_driver declaration leftover.
Reviewed-by: Krystian Pradzynski
Signed-off-by: Stanislaw Gruszka
Reviewed-by: Jeffrey Hugo
On 10/25/2023 3:43 AM, Stanislaw Gruszka wrote:
From: Krystian Pradzynski
Bump boot API to 4.20
Bump JSM API to 3.15
Signed-off-by: Krystian Pradzynski
Reviewed-by: Stanislaw Gruszka
Signed-off-by: Stanislaw Gruszka
---
drivers/accel/ivpu/ivpu_jsm_msg.c | 17 ++
On 10/27/23 09:17, Boris Brezillon wrote:
Hi Danilo,
On Thu, 26 Oct 2023 18:13:00 +0200
Danilo Krummrich wrote:
+
+ /**
+* @update_job_credits: Called once the scheduler is considering this
+* job for execution.
+*
+* Drivers may use this to update the
On 2023-10-27 04:25, Boris Brezillon wrote:
> Hi Danilo,
>
> On Thu, 26 Oct 2023 18:13:00 +0200
> Danilo Krummrich wrote:
>
>> Currently, job flow control is implemented simply by limiting the number
>> of jobs in flight. Therefore, a scheduler is initialized with a credit
>> limit that
Hi,
On Fri, Oct 27, 2023 at 5:30 AM Jonas Mark (BT-FS/ENG1-GRB)
wrote:
>
> > I think I've looked at this exact case before and then realized that
> > there's a better solution. At least in all cases I looked at the
> > "enable-gpio" you're talking about was actually better modeled as a
> >
On 10/27/23 10:25, Boris Brezillon wrote:
Hi Danilo,
On Thu, 26 Oct 2023 18:13:00 +0200
Danilo Krummrich wrote:
Currently, job flow control is implemented simply by limiting the number
of jobs in flight. Therefore, a scheduler is initialized with a credit
limit that corresponds to the number
On 10/24/2023 10:53 AM, Stanislaw Gruszka wrote:
From: Jacek Lawrynowicz
IP reset has to followed by ivpu_pll_disable() to properly enter
reset state.
Fixes: 828d63042aec ("accel/ivpu: Don't enter d0i3 during FLR")
Cc: sta...@vger.kernel.org
Signed-off-by: Jacek Lawrynowicz
Reviewed-by:
On Thursday, October 19th, 2023 at 23:21, Harry Wentland
wrote:
> +++ b/drivers/gpu/drm/vkms/Kconfig
> @@ -0,0 +1,15 @@
> +# SPDX-License-Identifier: GPL-2.0+
It seems like the original Kconfig uses GPL-2.0-only. I think it'd be
safer to just re-use the exact same license here?
With that
Have you seen the comment on top?
* Atomic drivers should never call this function directly, the core will read
* out property values through the various ->atomic_get_property callbacks.
It seems like atomic drivers shouldn't call drm_object_property_get_value()
at all?
Reviewed-by: Simon Ser
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