On 21/01/2024 20:41, Adam Skladowski wrote:
> During conversion 28nm-hpm-fam-b compat got lost, add it.
>
> Signed-off-by: Adam Skladowski
> ---
Acked-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On Mon, 22 Jan 2024 at 10:48, Krzysztof Kozlowski
wrote:
>
> On 21/01/2024 20:41, Adam Skladowski wrote:
> > During conversion 28nm-hpm-fam-b compat got lost, add it.
>
> Please add Fixes tag and put this commit as first in your patchset or
> even as separate one.
Fixes: f7d46c5efee2
If there is no VRAM (it can be true if there is a discreted card, this
is probably a hardware configuration issue in BIOS but it is observed in
GDC-1401 laptop, L71 laptop and some Loongson-3C5000L based servers), we
get such an error and Xorg fails to start:
[ 136.401131] loongson :00:06.1:
From: Keith Zhao
Add display bridge support for dsi on StarFive JH7110 SoC.
The mainly modification is followed:
1.Add extra clock and reset operation for JH7110.
2.Add callback for JH7110.
Signed-off-by: Keith Zhao
Signed-off-by: Shengyang Chen
---
This series is the series that attempts to support
the CDNS DSI driver used to converts DPI to DSI.
CDNS DSI is embedded in StarFive JH7110 SoC.
The series has been tested on the VisionFive 2 board.
change since v2:
- Rebased on tag v6.8-rc3.
patch 1:
- Modify commit message and patch subject
-
From: Keith Zhao
Add compatible to support dsi bridge on StarFive JH7110 SoC
Signed-off-by: Keith Zhao
Signed-off-by: Shengyang Chen
---
.../bindings/display/bridge/cdns,dsi.yaml | 56 ++-
1 file changed, 54 insertions(+), 2 deletions(-)
diff --git
On 2/5/24 20:43, Stephen Rothwell wrote:
> Hi all,
>
> Changes since 20240205:
>
Hi Rodrigo,
Are you aware of these kernel-doc warnings?
I think they are due to
commit b8c1c3a82e75
Author: Rodrigo Siqueira
Date: Mon Jan 22 14:24:57 2024 -0700
Documentation/gpu: Add kern
Hi all,
After merging the drm-misc tree, today's linux-next build (i386 defconfig)
failed like this:
In function 'i915_ttm_placement_from_obj',
inlined from 'i915_ttm_get_pages' at
drivers/gpu/drm/i915/gem/i915_gem_ttm.c:847:2:
drivers/gpu/drm/i915/gem/i915_gem_ttm.c:165:18: error:
On Sat, Feb 3, 2024 at 1:24 AM Sui Jingfeng wrote:
>
>
> On 2024/1/19 18:40, Huacai Chen wrote:
> > If there is no VRAM (it is true if there is a discreted card), we get
> > such an error and Xorg fails to start:
> >
> > [ 136.401131] loongson :00:06.1: [drm] *ERROR* Requesting(0MiB) failed
On Mon, Feb 5, 2024 at 2:17 AM Marco Felsch wrote:
>
> On 24-02-04, Dmitry Baryshkov wrote:
> > On Sat, 3 Feb 2024 at 17:53, Adam Ford wrote:
> > >
> > > From: Lucas Stach
> > >
> > > This adds the driver for the Samsung HDMI PHY found on the
> > > i.MX8MP SoC.
> > >
> > > Signed-off-by: Lucas
>From DT point of view, in general, drivers should be asking for a
specific port number because their function is fixed in the binding.
of_graph_get_next_endpoint() doesn't match to this concept.
Simply replace
- of_graph_get_next_endpoint(xxx, NULL);
+
>From DT point of view, in general, drivers should be asking for a
specific port number because their function is fixed in the binding.
of_graph_get_next_endpoint() doesn't match to this concept.
Simply replace
- of_graph_get_next_endpoint(xxx, NULL);
+
>From DT point of view, in general, drivers should be asking for a
specific port number because their function is fixed in the binding.
of_graph_get_next_endpoint() doesn't match to this concept.
Simply replace
- of_graph_get_next_endpoint(xxx, NULL);
+
>From DT point of view, in general, drivers should be asking for a
specific port number because their function is fixed in the binding.
of_graph_get_next_endpoint() doesn't match to this concept.
Simply replace
- of_graph_get_next_endpoint(xxx, NULL);
+
Hi Rob
We should get rid of or minimize of_graph_get_next_endpoint() in
its current form. In general, drivers should be asking for a specific
port number because their function is fixed in the binding.
https://lore.kernel.org/r/20240131184347.ga1906672-r...@kernel.org
This patch-set
On 1/23/2024 3:45 AM, Geert Uytterhoeven wrote:
> in drivers/net/ethernet/intel/ice/ice_base.c
>
> powerpc-gcc5/ppc32_allmodconfig
> in drivers/net/ethernet/intel/ice/ice_nvm.c
>
> aarcharm64-gcc5/arm64-allmodconfig
> powerpc-gcc5/ppc32_allmodconfig
> powerpc-gcc5/powerpc-allmodconfig
>
On Mon, Feb 5, 2024 at 1:26 AM Alexander Stein
wrote:
>
> Hi Adam,
>
> thanks for working on this.
>
> Am Samstag, 3. Februar 2024, 17:52:45 CET schrieb Adam Ford:
> > From: Lucas Stach
> >
> > This adds the PGC and HDMI blk-ctrl nodes providing power control for
> > HDMI subsystem peripherals.
On Tue, 16 Jan 2024 12:10:47 +0800, Li Zhijian wrote:
> make coccicheck COCCI=$PWD/scripts/coccinelle/api/device_attr_show.cocci`
> complians some warnnings as following[1]:
>
> Not sure if someone had tried these fixes, feel free to ignore this
> patch set if we have come to a *NOT-FIX*
On Tue, 6 Feb 2024 at 10:56, Luben Tuikov wrote:
>
> On 2024-02-05 08:33, Rodrigo Vivi wrote:
> > On Mon, Feb 05, 2024 at 09:44:56AM +0100, Christian König wrote:
> >> Am 02.02.24 um 22:58 schrieb Rodrigo Vivi:
> >>> On Tue, Jan 30, 2024 at 08:05:29AM +0100, Christian König wrote:
> Am
Hi all,
After merging the drm-misc tree, today's linux-next build (x86_64
allmodconfig) failed like this:
Caused by commit
a78a8da51b36 ("drm/ttm: replace busy placement with flags v6")
interacting with commit
dd08ebf6c352 ("drm/xe: Introduce a new DRM driver for Intel GPUs")
(and maybe
Hi all,
On Tue, 6 Feb 2024 11:59:56 +1100 Stephen Rothwell
wrote:
>
> Today's linux-next merge of the drm-misc tree got a conflict in:
>
> drivers/gpu/drm/bridge/samsung-dsim.c
>
> between commit:
>
> ff3d5d04db07 ("drm: bridge: samsung-dsim: Don't use FORCE_STOP_STATE")
>
> from Linus'
Hi all,
Today's linux-next merge of the drm-misc tree got a conflict in:
drivers/gpu/drm/bridge/samsung-dsim.c
between commit:
ff3d5d04db07 ("drm: bridge: samsung-dsim: Don't use FORCE_STOP_STATE")
from Linus' tree and commit:
b2fe2292624a ("drm: bridge: samsung-dsim: enter display
On 2024-02-05 08:33, Rodrigo Vivi wrote:
> On Mon, Feb 05, 2024 at 09:44:56AM +0100, Christian König wrote:
>> Am 02.02.24 um 22:58 schrieb Rodrigo Vivi:
>>> On Tue, Jan 30, 2024 at 08:05:29AM +0100, Christian König wrote:
Am 30.01.24 um 04:04 schrieb Matthew Brost:
> Rather then loop
On 2024-01-29 22:04, Matthew Brost wrote:
> Rather then loop over entities until one with a ready job is found,
> re-queue the run job worker when drm_sched_entity_pop_job() returns NULL.
>
> Fixes: 6dbd9004a55 ("drm/sched: Drain all entities in DRM sched run job
> worker")
> Signed-off-by:
On 2024-02-05 19:06, Luben Tuikov wrote:
> On 2024-02-01 07:56, Christian König wrote:
>> Am 31.01.24 um 18:11 schrieb Daniel Vetter:
>>> On Tue, Jan 30, 2024 at 07:03:02PM -0800, Matthew Brost wrote:
Add Matthew Brost to DRM scheduler maintainers.
Cc: Luben Tuikov
Cc: Daniel
On 2024-02-01 07:56, Christian König wrote:
> Am 31.01.24 um 18:11 schrieb Daniel Vetter:
>> On Tue, Jan 30, 2024 at 07:03:02PM -0800, Matthew Brost wrote:
>>> Add Matthew Brost to DRM scheduler maintainers.
>>>
>>> Cc: Luben Tuikov
>>> Cc: Daniel Vetter
>>> Cc: Dave Airlie
>>> Cc: Christian
Hi Rob
> I've read the threads already and think you should skip the rename. Just
> put 'port' in the name of the new one.
OK
> That and taking a port number param should be enough distinction.
I think we want to use "port" directly instead of "port number"
on new function.
Thank you for
From: Tobias Jakobi
Similar to the other Aya Neo devices this one features
again a portrait screen, here with a native resolution
of 1600x2560.
Signed-off-by: Tobias Jakobi
---
drivers/gpu/drm/drm_panel_orientation_quirks.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
On Sun, Feb 04, 2024 at 11:44:39PM +, Kuninori Morimoto wrote:
>
> Hi Rob
>
> > This is assuming there's just 1 port and 1 endpoint, but let's be
> > specific as the bindings are (first endpoint on port 0):
> >
> > of_graph_get_endpoint_by_regs(client->dev.of_node, 0, -1);
> >
> > Note we
On Tue, Jan 23, 2024 at 12:28:42PM +0200, Imre Deak wrote:
> +static int check_inherited_tunnel_state(struct intel_atomic_state *state,
> + struct intel_dp *intel_dp,
> + const struct
> intel_digital_connector_state
Hi Laurent,
Thanks a lot for the review.
> -Original Message-
> From: Laurent Pinchart
> Sent: Monday, February 5, 2024 12:08 AM
> To: Klymenko, Anatoliy
> Cc: maarten.lankho...@linux.intel.com; mrip...@kernel.org;
> tzimmerm...@suse.de; airl...@gmail.com; dan...@ffwll.ch; Simek,
On Mon, Feb 05, 2024 at 07:15:17PM +0200, Imre Deak wrote:
> On Mon, Feb 05, 2024 at 06:13:30PM +0200, Ville Syrjälä wrote:
> > On Wed, Jan 31, 2024 at 08:49:16PM +0200, Imre Deak wrote:
> > > On Wed, Jan 31, 2024 at 06:09:04PM +0200, Ville Syrjälä wrote:
> > > > On Tue, Jan 23, 2024 at 12:28:33PM
On 2/5/24 22:08, Dave Airlie wrote:
On Tue, 6 Feb 2024 at 02:22, Danilo Krummrich wrote:
On 1/29/24 02:50, Dave Airlie wrote:
From: Dave Airlie
This should break the deadlock between the fctx lock and the irq lock.
This offloads the processing off the work from the irq into a workqueue.
0.o := $(dml_ccflags)
$(frame_warn_flag)
CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_ccflags)
---
base-commit: 6813cdca4ab94a238f8eb0cef3d3f3fcbdfb0ee0
change-id: 20240205-amdgpu-raise-flt-for-dml-vba-files-ee5b5a9c5e43
Best regards,
--
Nathan Chancellor
On Tue, 6 Feb 2024 at 02:22, Danilo Krummrich wrote:
>
> On 1/29/24 02:50, Dave Airlie wrote:
> > From: Dave Airlie
> >
> > This should break the deadlock between the fctx lock and the irq lock.
> >
> > This offloads the processing off the work from the irq into a workqueue.
> >
> >
On 2024-02-05 at 18:56:09 +0100, Jernej Škrabec
wrote:
> Dne ponedeljek, 05. februar 2024 ob 16:22:26 CET je Frank Oltmanns napisal(a):
>> According to the Allwinner User Manual, the Allwinner A64 requires
>> PLL-MIPI to run at 500MHz-1.4GHz. Add support for that to ccu_nkm.
>>
>>
On Fri, Jan 12, 2024 at 5:13 AM Daniel Vetter wrote:
>
> On Sun, Dec 24, 2023 at 02:29:24AM +0800, Jason-JH.Lin wrote:
> > Add secure buffer control flow to mtk_drm_gem.
> >
> > When user space takes DRM_MTK_GEM_CREATE_ENCRYPTED flag and size
> > to create a mtk_drm_gem object, mtk_drm_gem will
On Mon, 05 Feb 2024 16:36:06 +0530, Dharma Balasubiramani wrote:
> Add the 'sam9x75-lvds' compatible binding, which describes the Low Voltage
> Differential Signaling (LVDS) Controller found on some Microchip's sam9x7
> series System-on-Chip (SoC) devices. This binding will be used to define
>
On Sat, 03 Feb 2024 10:52:49 -0600, Adam Ford wrote:
> From: Lucas Stach
>
> The HDMI TX controller on the i.MX8MP SoC is a Synopsys designware IP
> core with a little bit of SoC integration around it.
>
> Signed-off-by: Lucas Stach
> Signed-off-by: Adam Ford
>
> ---
> V3: Change name and
On Sat, 03 Feb 2024 10:52:43 -0600, Adam Ford wrote:
> Per guidance from the NXP downstream kernel, if the clock is
> disabled before HDMI/LCDIF probe, LCDIF will not get pixel
> clock from HDMI PHY and throw an error:
>
> [CRTC:39:crtc-2] vblank wait timed out
> WARNING: CPU: 2 PID: 9 at
Hi,
On Fri, Feb 2, 2024 at 12:25 PM Jeffrey Hugo wrote:
>
> The servers for the @codeaurora domain are long retired and any messages
> sent there bounce. Sandeep Panda's email address is no longer valid and
> should be repleaced. However Sandeep has left the company and has not
> been active
On Fri, 02 Feb 2024 13:23:29 -0700, Jeffrey Hugo wrote:
> The servers for the @codeaurora domain are long retired and any messages
> sent there bounce. Sandeep Panda's email address is no longer valid and
> should be repleaced. However Sandeep has left the company and has not
> been active
On Fri, 02 Feb 2024 11:01:51 -0700, Jeffrey Hugo wrote:
> Bjorn is no longer at Linaro. Update his email address to @kernel to
> match the .mailmap entry.
>
> The servers for @codeaurora are long retired and messages sent there
> will bounce. Update Kiran's email address to match the .mailmap
Hi,
On Mon, Feb 5, 2024 at 12:13 AM Markus Elfring wrote:
>
> From: Markus Elfring
> Date: Mon, 5 Feb 2024 08:58:21 +0100
>
> A wrapper function is available since the commit
> 890cc39a879906b63912482dfc41944579df2dc6
> ("drivers: provide devm_platform_get_and_ioremap_resource()").
> Thus
Dne ponedeljek, 05. februar 2024 ob 16:22:28 CET je Frank Oltmanns napisal(a):
> This panel is used in the pinephone that runs on a Allwinner A64 SOC.
> The SOC requires pll-mipi to run at more than 500 MHz.
>
> This is the relevant clock tree:
> pll-mipi
> tcon0
>tcon-data-clock
>
Dne ponedeljek, 05. februar 2024 ob 16:22:27 CET je Frank Oltmanns napisal(a):
> Set the minimum and maximum rate of Allwinner A64's PLL-MIPI according
> to the Allwinner User Manual.
>
> Signed-off-by: Frank Oltmanns
Reviewed-by: Jernej Skrabec
Best regards,
Jernej
Dne ponedeljek, 05. februar 2024 ob 16:22:26 CET je Frank Oltmanns napisal(a):
> According to the Allwinner User Manual, the Allwinner A64 requires
> PLL-MIPI to run at 500MHz-1.4GHz. Add support for that to ccu_nkm.
>
> Signed-off-by: Frank Oltmanns
> ---
> drivers/clk/sunxi-ng/ccu_nkm.c | 13
On Mon, Feb 5, 2024 at 12:13 AM Markus Elfring wrote:
>
> From: Markus Elfring
> Date: Mon, 5 Feb 2024 08:58:21 +0100
>
> A wrapper function is available since the commit
> 890cc39a879906b63912482dfc41944579df2dc6
> ("drivers: provide devm_platform_get_and_ioremap_resource()").
> Thus reuse
Disable the px_clk when setting the rate to recover a fully
configured and correctly reset VCLK clock tree after the rate
is set.
Fixes: 77d9e1e6b846 ("drm/meson: add support for MIPI-DSI transceiver")
Signed-off-by: Neil Armstrong
---
drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 7 +++
1
This adds a basic devicetree for the MNT Reform2 DIY laptop when using a
CM4 adapter and a BPI-CM4 module.
Co-developed-by: Lukas F. Hartmann
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/Makefile | 1 +
.../meson-g12b-bananapi-cm4-mnt-reform2.dts| 384
This add dtbo overlay to support the Khadas TS050 panel on the
Khadas VIM3 & VIM3L boards.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/Makefile | 3 +
.../boot/dts/amlogic/meson-khadas-vim3-ts050.dtso | 108 +
2 files changed, 111
Add the MIPI DSI Analog & Digital PHY nodes and the DSI control
nodes with proper port endpoint to the VPU.
Signed-off-by: Neil Armstrong
---
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 70 +++
1 file changed, 70 insertions(+)
diff --git
The VCLK and VCLK_DIV clocks have supplementary bits.
The VCLK gate has a "SOFT RESET" bit to toggle after the whole
VCLK sub-tree rate has been set, this is implemented in
the gate enable callback.
The VCLK_DIV clocks as enable and reset bits used to disable
and reset the divider, associated
In order to setup the DSI clock, let's make the unused VCLK2 clock path
configuration via CCF.
The nocache option is removed from following clocks:
- vclk2_sel
- vclk2_input
- vclk2_div
- vclk2
- vclk_div1
- vclk2_div2_en
- vclk2_div4_en
- vclk2_div6_en
- vclk2_div12_en
- vclk2_div2
- vclk2_div4
The MNT Reform 2 CM4 adapter can be populated with any Raspberry Pi CM4
compatible module such as a BPI-CM4 Module, document that.
Acked-by: Conor Dooley
Signed-off-by: Neil Armstrong
---
Documentation/devicetree/bindings/arm/amlogic.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver
(ver 1.21a),
with a custom glue managing the IP resets, clock and data input similar to the
DW-HDMI
glue on the same Amlogic SoCs.
This is a follow-up of v5 now the DRM patches are applied, the clk & DT changes
remains
On Mon, Feb 05, 2024 at 06:11:00PM +0200, Ville Syrjälä wrote:
> On Tue, Jan 23, 2024 at 12:28:43PM +0200, Imre Deak wrote:
> > Add the atomic state during a modeset required to enable the DP tunnel
> > BW allocation mode on links where such a tunnel was detected.
> >
> > Signed-off-by: Imre Deak
Hi Jernej,
On 2024-02-05 at 18:45:27 +0100, Jernej Škrabec
wrote:
> Dne ponedeljek, 05. februar 2024 ob 16:22:24 CET je Frank Oltmanns napisal(a):
>> The Allwinner A64 manual lists the following constraints for the
>> PLL-MIPI clock:
>> - M/N <= 3
>> - (PLL_VIDEO0)/M >= 24MHz
>>
>> The
Dne ponedeljek, 05. februar 2024 ob 16:22:24 CET je Frank Oltmanns napisal(a):
> The Allwinner A64 manual lists the following constraints for the
> PLL-MIPI clock:
> - M/N <= 3
> - (PLL_VIDEO0)/M >= 24MHz
>
> The PLL-MIPI clock is implemented as ccu_nkm. Therefore, add support for
> these
On 27/11/2023 17:24, Jerome Brunet wrote:
On Mon 27 Nov 2023 at 17:14, Neil Armstrong wrote:
On 24/11/2023 15:41, Jerome Brunet wrote:
On Fri 24 Nov 2023 at 09:41, Neil Armstrong
wrote:
The VCLK and VCLK_DIV clocks have supplementary bits.
The VCLK has a "SOFT RESET" bit to toggle after
On Mon, Feb 05, 2024 at 06:13:30PM +0200, Ville Syrjälä wrote:
> On Wed, Jan 31, 2024 at 08:49:16PM +0200, Imre Deak wrote:
> > On Wed, Jan 31, 2024 at 06:09:04PM +0200, Ville Syrjälä wrote:
> > > On Tue, Jan 23, 2024 at 12:28:33PM +0200, Imre Deak wrote:
> > > > +static void
On 1/30/24 04:26, Dave Airlie wrote:
From: Dave Airlie
Timur pointed this out before, and it just slipped my mind,
but this might help some things work better, around pcie power
management.
Fixes: 8d55b0a940bb ("nouveau/gsp: add some basic registry entries.")
Signed-off-by: Dave Airlie
Hi,
On Mon, Feb 5, 2024 at 3:17 AM Jani Nikula wrote:
>
> On Fri, 02 Feb 2024, Douglas Anderson wrote:
> > If an eDP panel is not powered on then any attempts to talk to it over
> > the DP AUX channel will timeout. Unfortunately these attempts may be
> > quite slow. Userspace can initiate these
On 1/29/24 02:50, Dave Airlie wrote:
From: Dave Airlie
This should break the deadlock between the fctx lock and the irq lock.
This offloads the processing off the work from the irq into a workqueue.
Signed-off-by: Dave Airlie
Nouveau's scheduler uses a dedicated wq, hence from this
Hi mac.shen,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on pza/reset/next linus/master v6.8-rc3 next-20240205]
[cannot apply to pza/imx-drm/next]
[If your patch is applied to the wrong git tree, kindly drop
On Wed, Jan 31, 2024 at 08:49:16PM +0200, Imre Deak wrote:
> On Wed, Jan 31, 2024 at 06:09:04PM +0200, Ville Syrjälä wrote:
> > On Tue, Jan 23, 2024 at 12:28:33PM +0200, Imre Deak wrote:
> > > +static void untrack_tunnel_ref(struct drm_dp_tunnel *tunnel,
> > > +struct
On Tue, Jan 23, 2024 at 12:28:43PM +0200, Imre Deak wrote:
> Add the atomic state during a modeset required to enable the DP tunnel
> BW allocation mode on links where such a tunnel was detected.
>
> Signed-off-by: Imre Deak
> ---
> drivers/gpu/drm/i915/display/intel_atomic.c | 8
>
amdgpu_irq_ad_id() may fail and the irq handlers will not be registered.
This patch adds error code check.
Found by Linux Verification Center (linuxtesting.org).
Signed-off-by: Igor Artemiev
---
v2: Free the source as Alexey Khoroshilov suggested.
.../drm/amd/pm/powerplay/hwmgr/smu_helper.c
On Mon, Feb 05, 2024 at 04:54:07PM +0100, Ondřej Jirman wrote:
> On Mon, Feb 05, 2024 at 04:22:23PM +0100, Frank Oltmanns wrote:
> > On some pinephones the video output sometimes freezes (flips between two
> > frames) [1]. It seems to be that the reason for this behaviour is that
> > PLL-MIPI,
On Mon, Feb 05, 2024 at 04:22:23PM +0100, Frank Oltmanns wrote:
> On some pinephones the video output sometimes freezes (flips between two
> frames) [1]. It seems to be that the reason for this behaviour is that
> PLL-MIPI, PLL-GPU and GPU are operating outside their limits.
>
> In this patch
Set the minimum and maximum rate of Allwinner A64's PLL-MIPI according
to the Allwinner User Manual.
Signed-off-by: Frank Oltmanns
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
The PLL-GPU has a minimum rate of 192 MHz according to the A64 manual.
If run at less than 192 MHz the pinephone (based on the A64) sometimes
replays the last few frames that were displayed over and over (see first
link below).
Note, that running PLL-GPU at 240 MHz and using a divisor of 2
According to the Allwinner User Manual, the Allwinner A64 requires
PLL-MIPI to run at 500MHz-1.4GHz. Add support for that to ccu_nkm.
Signed-off-by: Frank Oltmanns
---
drivers/clk/sunxi-ng/ccu_nkm.c | 13 +
drivers/clk/sunxi-ng/ccu_nkm.h | 2 ++
2 files changed, 15 insertions(+)
This panel is used in the pinephone that runs on a Allwinner A64 SOC.
The SOC requires pll-mipi to run at more than 500 MHz.
This is the relevant clock tree:
pll-mipi
tcon0
tcon-data-clock
tcon-data-clock has to run at 1/4 the DSI per-lane bit rate. The XBD599
has 24 bpp and 4 lanes.
The Allwinner A64 manual lists the following constraints for the
PLL-MIPI clock:
- M/N <= 3
- (PLL_VIDEO0)/M >= 24MHz
The PLL-MIPI clock is implemented as ccu_nkm. Therefore, add support for
these constraints.
Signed-off-by: Frank Oltmanns
---
drivers/clk/sunxi-ng/ccu_nkm.c | 21
On some pinephones the video output sometimes freezes (flips between two
frames) [1]. It seems to be that the reason for this behaviour is that
PLL-MIPI, PLL-GPU and GPU are operating outside their limits.
In this patch series I propose the followin changes:
1. sunxi-ng: Adhere to the following
The Allwinner A64 manual lists the following constraints for the
PLL-MIPI clock:
- M/N <= 3
- (PLL_VIDEO0)/M >= 24MHz
Use these constraints.
Signed-off-by: Frank Oltmanns
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
diff --git
On 01/26, Alex Hung wrote:
>
>
> On 2024-01-26 09:28, Melissa Wen wrote:
> > Replace raw edid handling (struct edid) with the opaque EDID type
> > (struct drm_edid) on amdgpu_dm_connector for consistency. It may also
> > prevent mismatch of approaches in different parts of the driver code.
> >
On 01/29, Jani Nikula wrote:
> On Fri, 26 Jan 2024, Mario Limonciello wrote:
> > On 1/26/2024 10:28, Melissa Wen wrote:
> >> Hi,
> >>
> >> I'm debugging a null-pointer dereference when running
> >> igt@kms_connector_force_edid and the way I found to solve the bug is to
> >> stop using raw edid
On Sat, Feb 03, 2024 at 03:55:54AM +0100, Dmitry Baryshkov wrote:
> On Fri, 2 Feb 2024 at 23:23, Rob Herring wrote:
> >
> > In order to check schemas for missing additionalProperties or
> > unevaluatedProperties, cases allowing extra properties must be explicit.
> >
> > Signed-off-by: Rob Herring
On 05.02.2024 15:25, Igor Artemiev wrote:
> amdgpu_irq_ad_id() may fail and the irq handlers will not be registered.
> This patch adds error code check.
But what is about deallocation of already allocated memory?
--
Alexey
On Mon, Feb 05, 2024 at 09:44:56AM +0100, Christian König wrote:
> Am 02.02.24 um 22:58 schrieb Rodrigo Vivi:
> > On Tue, Jan 30, 2024 at 08:05:29AM +0100, Christian König wrote:
> > > Am 30.01.24 um 04:04 schrieb Matthew Brost:
> > > > Rather then loop over entities until one with a ready job is
Hi Greg,
Thanks for your inputs and patience in reviewing the patch.
By mistakenly this internal patch has been sent for review as the reference
commit ID is from opensource, email has been sent to those who are all involved
in that commit.
Please ignore this patch as it is for internal usage.
On 05/02/2024 at 12:06, Dharma B - I70843 wrote:
Enable LVDS serializer support for display pipeline.
Signed-off-by: Dharma Balasubiramani
Acked-by: Hari Prasath Gujulan Elango
Acked-by: Nicolas Ferre
---
arch/arm/configs/at91_dt_defconfig | 1 +
1 file changed, 1 insertion(+)
diff
On 05/02/2024 at 12:06, Dharma B - I70843 wrote:
Add the newly added LVDS controller for the SAM9X7 SoC to the existing
MAINTAINERS entry.
Signed-off-by: Dharma Balasubiramani
If new series is to be done, this entry should be placed before this one
"MICROCHIP SAMA5D2-COMPATIBLE ADC DRIVER"
amdgpu_irq_ad_id() may fail and the irq handlers will not be registered.
This patch adds error code check.
Found by Linux Verification Center (linuxtesting.org).
Signed-off-by: Igor Artemiev
---
.../gpu/drm/amd/pm/powerplay/hwmgr/smu_helper.c| 14 +++---
1 file changed, 11
Hi
Am 05.02.24 um 11:05 schrieb Sui Jingfeng:
Hi,
On 2024/2/5 16:17, Thomas Zimmermann wrote:
Hi
Am 02.02.24 um 18:03 schrieb Sui Jingfeng:
Hi,
On 2024/2/2 19:58, Thomas Zimmermann wrote:
+
+/**
+ * screen_info_pci_dev() - Return PCI parent device that contains
screen_info's framebuffer
Hi,
On Sat, 03 Feb 2024 10:52:40 -0600, Adam Ford wrote:
> The i.MX8M Plus has an HDMI controller, but it depends on two
> other systems, the Parallel Video Interface (PVI) and the
> HDMI PHY from Samsung. The LCDIF controller generates the display
> and routes it to the PVI which converts passes
Hi,
On Fri, 02 Feb 2024 13:50:21 -0800, Jessica Zhang wrote:
> The DSI host needs to be enabled for the panel to be initialized in
> prepare(). Ensure this happens by setting prepare_prev_first.
>
>
Thanks, Applied to https://anongit.freedesktop.org/git/drm/drm-misc.git
(drm-misc-next)
[1/1]
On 03/02/2024 17:52, Adam Ford wrote:
From: Lucas Stach
The HDMI TX controller on the i.MX8MP SoC is a Synopsys designware IP
core with a little bit of SoC integration around it.
Signed-off-by: Lucas Stach
Signed-off-by: Adam Ford
---
V3: Change name and location to better idenfity as a
On Fri, 02 Feb 2024, Douglas Anderson wrote:
> If an eDP panel is not powered on then any attempts to talk to it over
> the DP AUX channel will timeout. Unfortunately these attempts may be
> quite slow. Userspace can initiate these attempts either via a
> /dev/drm_dp_auxN device or via the
On 05/02/2024 12:06, Dharma Balasubiramani wrote:
Add the newly added LVDS controller for the SAM9X7 SoC to the existing
MAINTAINERS entry.
Signed-off-by: Dharma Balasubiramani
---
Changelog
v1 -> v2
- No Changes.
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git
Hi,
On 05/02/2024 12:06, Dharma Balasubiramani wrote:
Add a new LVDS controller driver for sam9x7 which does the following:
- Prepares and enables the LVDS Peripheral clock
- Defines its connector type as DRM_MODE_CONNECTOR_LVDS and adds itself
to the global bridge list.
- Identifies its output
Add the 'sam9x75-lvds' compatible binding, which describes the Low Voltage
Differential Signaling (LVDS) Controller found on some Microchip's sam9x7
series System-on-Chip (SoC) devices. This binding will be used to define
the properties and configuration for the LVDS Controller in DT.
Enable LVDS serializer support for display pipeline.
Signed-off-by: Dharma Balasubiramani
Acked-by: Hari Prasath Gujulan Elango
---
arch/arm/configs/at91_dt_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/at91_dt_defconfig
b/arch/arm/configs/at91_dt_defconfig
Add the newly added LVDS controller for the SAM9X7 SoC to the existing
MAINTAINERS entry.
Signed-off-by: Dharma Balasubiramani
---
Changelog
v1 -> v2
- No Changes.
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
This patch series introduces LVDS controller support for the SAM9X75 SoC. The
LVDS controller is designed to work with Microchip's sam9x7 series
System-on-Chip (SoC) devices, providing Low Voltage Differential Signaling
capabilities.
Patch series Changelog:
- Include configs: at91: Enable LVDS
Add a new LVDS controller driver for sam9x7 which does the following:
- Prepares and enables the LVDS Peripheral clock
- Defines its connector type as DRM_MODE_CONNECTOR_LVDS and adds itself
to the global bridge list.
- Identifies its output endpoint as panel and adds it to the encoder
display
On Mon, 5 Feb 2024 10:54:05 +0100
Danilo Krummrich wrote:
> On 2/5/24 10:03, Boris Brezillon wrote:
> > +Danilo for the panthor gpuvm-needs update.
> >
> > On Sun, 4 Feb 2024 09:14:44 +0800 (CST)
> > "Andy Yan" wrote:
> >
> >> Hi Boris：
> >> I saw this warning sometimes（Run on a armbain
From: Markus Elfring
Date: Mon, 5 Feb 2024 11:16:27 +0100
A wrapper function is available since the commit
890cc39a879906b63912482dfc41944579df2dc6
("drivers: provide devm_platform_get_and_ioremap_resource()").
Thus reuse existing functionality instead of keeping duplicate source code.
This
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