On 6/14/2023 5:23 AM, Marijn Suijten wrote:
On 2023-06-14 15:01:59, Dmitry Baryshkov wrote:
On 14/06/2023 14:42, Marijn Suijten wrote:
On 2023-06-13 18:57:11, Jessica Zhang wrote:
DPU 5.x+ supports a databus widen mode that allows more data to be sent
per pclk. Enable this feature flag on a
On 6/14/2023 12:35 PM, Abhinav Kumar wrote:
On 6/14/2023 5:23 AM, Marijn Suijten wrote:
On 2023-06-14 15:01:59, Dmitry Baryshkov wrote:
On 14/06/2023 14:42, Marijn Suijten wrote:
On 2023-06-13 18:57:11, Jessica Zhang wrote:
DPU 5.x+ supports a databus widen mode that allows more data to
On 6/14/2023 12:54 PM, Abhinav Kumar wrote:
On 6/14/2023 12:35 PM, Abhinav Kumar wrote:
On 6/14/2023 5:23 AM, Marijn Suijten wrote:
On 2023-06-14 15:01:59, Dmitry Baryshkov wrote:
On 14/06/2023 14:42, Marijn Suijten wrote:
On 2023-06-13 18:57:11, Jessica Zhang wrote:
DPU 5.x+ supports
On 6/14/2023 3:49 PM, Marijn Suijten wrote:
On 2023-06-14 14:23:38, Marijn Suijten wrote:
Tested this on SM8350 which actually has DSI 2.5, and it is also
corrupted with this series so something else on this series might be
broken.
Never mind, this was a bad conflict-resolve. Jessica's or
On 6/14/2023 1:43 PM, Dmitry Baryshkov wrote:
On 14/06/2023 23:39, Abhinav Kumar wrote:
On 6/14/2023 12:54 PM, Abhinav Kumar wrote:
On 6/14/2023 12:35 PM, Abhinav Kumar wrote:
On 6/14/2023 5:23 AM, Marijn Suijten wrote:
On 2023-06-14 15:01:59, Dmitry Baryshkov wrote:
On 14/06/2023
On 6/14/2023 2:41 PM, Marijn Suijten wrote:
On 2023-06-14 13:39:57, Abhinav Kumar wrote:
On 6/14/2023 12:54 PM, Abhinav Kumar wrote:
On 6/14/2023 12:35 PM, Abhinav Kumar wrote:
On 6/14/2023 5:23 AM, Marijn Suijten wrote:
On 2023-06-14 15:01:59, Dmitry Baryshkov wrote:
On 14/06/2023 14:42
On 6/14/2023 12:56 AM, Dmitry Baryshkov wrote:
On 14/06/2023 04:57, Jessica Zhang wrote:
Add a DPU INTF op to set the DATABUS_WIDEN register to enable the
databus-widen mode datapath.
Signed-off-by: Jessica Zhang
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 3 +++
drivers/
On 6/14/2023 12:49 AM, Dmitry Baryshkov wrote:
On 14/06/2023 04:57, Jessica Zhang wrote:
DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send
48 bits of compressed data per pclk instead of 24.
For all chipsets that support this mode, enable it whenever DSC is
enabled as reco
On 6/21/2023 9:36 AM, Dmitry Baryshkov wrote:
On 21/06/2023 18:17, Marijn Suijten wrote:
On 2023-06-20 14:38:34, Jessica Zhang wrote:
+ if (phys_enc->hw_intf->ops.enable_widebus)
+ phys_enc->hw_intf->ops.enable_widebus(phys_enc->hw_intf);
No. Please provide a single function whi
On 6/22/2023 7:00 AM, Dmitry Baryshkov wrote:
On 21/06/2023 19:18, Kuogee Hsieh wrote:
Currently DSI DSC struct is populated at display setup during
system bootup. This mechanism works fine with embedded display
but not for pluggable displays as the DSC struct will become
stale once external
On 6/21/2023 4:46 PM, Dmitry Baryshkov wrote:
On 22/06/2023 02:01, Abhinav Kumar wrote:
On 6/21/2023 9:36 AM, Dmitry Baryshkov wrote:
On 21/06/2023 18:17, Marijn Suijten wrote:
On 2023-06-20 14:38:34, Jessica Zhang wrote:
+ if (phys_enc->hw_intf->ops.enable_w
On 6/14/2023 3:03 AM, Marijn Suijten wrote:
On 2023-06-14 10:49:31, Dmitry Baryshkov wrote:
On 14/06/2023 04:57, Jessica Zhang wrote:
DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send
48 bits of compressed data per pclk instead of 24.
For all chipsets that support this m
On 6/22/2023 4:14 PM, Dmitry Baryshkov wrote:
On 23/06/2023 01:37, Abhinav Kumar wrote:
On 6/21/2023 4:46 PM, Dmitry Baryshkov wrote:
On 22/06/2023 02:01, Abhinav Kumar wrote:
On 6/21/2023 9:36 AM, Dmitry Baryshkov wrote:
On 21/06/2023 18:17, Marijn Suijten wrote:
On 2023-06-20 14:38
On 6/14/2023 2:56 AM, Marijn Suijten wrote:
On 2023-06-13 18:57:13, Jessica Zhang wrote:
DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send
48 bits of compressed data per pclk instead of 24.
For all chipsets that support this mode, enable it whenever DSC is
enabled as reco
On 6/19/2023 2:06 PM, Dmitry Baryshkov wrote:
Provide actual documentation for the pclk and hdisplay calculations in
the case of DSC compression being used.
Signed-off-by: Dmitry Baryshkov
---
Changes since v1:
- Converted dsi_adjust_pclk_for_compression() into kerneldoc (Marijn)
- Added a
On 6/22/2023 5:17 PM, Dmitry Baryshkov wrote:
On 23/06/2023 03:14, Abhinav Kumar wrote:
On 6/19/2023 2:06 PM, Dmitry Baryshkov wrote:
Provide actual documentation for the pclk and hdisplay calculations in
the case of DSC compression being used.
Signed-off-by: Dmitry Baryshkov
On 6/22/2023 6:37 PM, Dmitry Baryshkov wrote:
All DSC_BLK_1_2 declarations incorrectly pass 0x29c as the block length.
This includes the common block itself, enc subblocks and some empty
space around. Change that to pass 0x4 instead, the length of common
register block itself.
Fixes: 0d1b10c6
On 6/23/2023 12:19 AM, Marijn Suijten wrote:
On 2023-06-22 17:01:34, Abhinav Kumar wrote:
More interesting would be a link to the Mesa MR upstreaming this
bitfield to dsi.xml [2] (which I have not found on my own yet).
[2]:
https://gitlab.freedesktop.org/mesa/mesa/-/blame/main/src
On 6/23/2023 4:25 AM, Dmitry Baryshkov wrote:
On 23/06/2023 08:47, Abhinav Kumar wrote:
On 6/22/2023 6:37 PM, Dmitry Baryshkov wrote:
All DSC_BLK_1_2 declarations incorrectly pass 0x29c as the block length.
This includes the common block itself, enc subblocks and some empty
space around
On 6/23/2023 6:58 AM, Dmitry Baryshkov wrote:
Ryan pointed out [1] that some (most) of of sub-blocks do not fill the
field `name'. Further research showed that we can drop the fields `name'
and `id' and further simplify the catalog. The handling code also
usually knows, which sub-block it is n
On 6/22/2023 11:57 PM, Marijn Suijten wrote:
On 2023-06-23 08:54:39, Marijn Suijten wrote:
On 2023-06-22 22:47:04, Abhinav Kumar wrote:
On 6/22/2023 6:37 PM, Dmitry Baryshkov wrote:
All DSC_BLK_1_2 declarations incorrectly pass 0x29c as the block length.
This includes the common block
On 6/23/2023 4:37 AM, Dmitry Baryshkov wrote:
On 23/06/2023 09:54, Marijn Suijten wrote:
On 2023-06-22 22:47:04, Abhinav Kumar wrote:
On 6/22/2023 6:37 PM, Dmitry Baryshkov wrote:
All DSC_BLK_1_2 declarations incorrectly pass 0x29c as the block
length.
This includes the common block
On 6/23/2023 12:40 PM, Dmitry Baryshkov wrote:
On 23/06/2023 22:37, Abhinav Kumar wrote:
On 6/23/2023 4:37 AM, Dmitry Baryshkov wrote:
On 23/06/2023 09:54, Marijn Suijten wrote:
On 2023-06-22 22:47:04, Abhinav Kumar wrote:
On 6/22/2023 6:37 PM, Dmitry Baryshkov wrote:
All DSC_BLK_1_2
On 6/23/2023 12:26 AM, Marijn Suijten wrote:
On 2023-06-22 17:32:17, Abhinav Kumar wrote:
On 6/22/2023 5:17 PM, Dmitry Baryshkov wrote:
On 23/06/2023 03:14, Abhinav Kumar wrote:
On 6/19/2023 2:06 PM, Dmitry Baryshkov wrote:
Provide actual documentation for the pclk and hdisplay
On 6/23/2023 1:14 PM, Marijn Suijten wrote:
On 2023-06-23 10:29:51, Abhinav Kumar wrote:
The concept is quite simple
one pixel per clock for uncompresssed without widebubus
2 pixels per clock for uncompressed with widebus (only enabled for DP
not DSI)
3 bytes worth of data for compressed
On 6/23/2023 2:33 PM, Marijn Suijten wrote:
On 2023-06-23 13:34:06, Abhinav Kumar wrote:
On 6/23/2023 1:14 PM, Marijn Suijten wrote:
On 2023-06-23 10:29:51, Abhinav Kumar wrote:
The concept is quite simple
one pixel per clock for uncompresssed without widebubus
2 pixels per clock for
On 6/23/2023 1:28 PM, Marijn Suijten wrote:
On 2023-06-23 14:37:12, Dmitry Baryshkov wrote:
In fact I asked to make it 0xf00 + 0x10 or 0xf80 + 0x10 to also cover
the CTL registers, but that change didn't make it through. 0x29c is an
arbitrary number that I have no clue what it was based on.
On 6/23/2023 1:18 PM, Marijn Suijten wrote:
On 2023-06-23 23:10:56, Dmitry Baryshkov wrote:
There is no confusion between what was said earlier and now.
This line is calculating the number of pclks needed to transmit one line
of the compressed data:
hdisplay = DIV_ROUND_UP(msm_dsc_get_byte
On 6/22/2023 5:13 PM, Dmitry Baryshkov wrote:
On 23/06/2023 02:48, Ryan McCann wrote:
Currently, the device core dump mechanism does not dump registers of sub
blocks within the DSPP, SSPP, DSC, and PINGPONG blocks. Add wrapper
function to dump hardware blocks that contain sub blocks.
Signed-
On 6/24/2023 5:07 AM, Dmitry Baryshkov wrote:
On 24/06/2023 03:09, Abhinav Kumar wrote:
On 6/22/2023 5:13 PM, Dmitry Baryshkov wrote:
On 23/06/2023 02:48, Ryan McCann wrote:
Currently, the device core dump mechanism does not dump registers of
sub
blocks within the DSPP, SSPP, DSC, and
On 6/24/2023 8:03 AM, Dmitry Baryshkov wrote:
On 24/06/2023 17:17, Abhinav Kumar wrote:
On 6/24/2023 5:07 AM, Dmitry Baryshkov wrote:
On 24/06/2023 03:09, Abhinav Kumar wrote:
On 6/22/2023 5:13 PM, Dmitry Baryshkov wrote:
On 23/06/2023 02:48, Ryan McCann wrote:
Currently, the device
On 6/27/2023 2:59 PM, Dmitry Baryshkov wrote:
On 28/06/2023 00:27, Jessica Zhang wrote:
On 6/27/2023 12:58 AM, Pekka Paalanen wrote:
On Mon, 26 Jun 2023 16:02:50 -0700
Jessica Zhang wrote:
On 11/7/2022 11:37 AM, Ville Syrjälä wrote:
On Fri, Oct 28, 2022 at 03:59:49PM -0700, Jessica Zha
On 6/26/2023 7:04 AM, Dmitry Baryshkov wrote:
On 24/06/2023 03:41, Marijn Suijten wrote:
SM6125 is identical to SM6375 except that while downstream also defines
a throttle clock, its presence results in timeouts whereas SM6375
requires it to not observe any timeouts.
I see that the vendor D
On 6/22/2023 4:37 PM, Abhinav Kumar wrote:
On 6/22/2023 4:14 PM, Dmitry Baryshkov wrote:
On 23/06/2023 01:37, Abhinav Kumar wrote:
On 6/21/2023 4:46 PM, Dmitry Baryshkov wrote:
On 22/06/2023 02:01, Abhinav Kumar wrote:
On 6/21/2023 9:36 AM, Dmitry Baryshkov wrote:
On 21/06/2023 18
and allow it to accept a struct intf_dpu_datapath_cfg to program
all the bits at once. This can be re-used by widebus later on as
well as it touches the same register.
Signed-off-by: Abhinav Kumar
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 9 +++--
drivers/gpu/drm/msm
Now that all usages of DPU_INTF_DATA_COMPRESS have been replaced
with the dpu core's major revision lets drop DPU_INTF_DATA_COMPRESS
from the catalog completely.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
drivers/gpu/drm/msm/disp
ktop.org/patch/530891/?series=113910&rev=4
changes in v2:
- drop DPU step version as features are not changing across steps
- add core_major_version / core_minor_version to avoid conflicts
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.
and allow it to accept a struct intf_dpu_datapath_cfg to program
all the bits at once. This can be re-used by widebus later on as
well as it touches the same register.
Signed-off-by: Abhinav Kumar
---
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 9 +++--
drivers/gpu/drm/msm
ork.freedesktop.org/patch/530891/?series=113910&rev=4
changes in v3:
- drop DPU step version as features are not changing across steps
- add core_major_version / core_minor_version to avoid conflicts
- update the commit text to drop references to the dpu macros
Signe
Now that all usages of DPU_INTF_DATA_COMPRESS have been replaced
with the dpu core's major revision lets drop DPU_INTF_DATA_COMPRESS
from the catalog completely.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 +-
drivers/gpu/drm/msm/disp
On 6/24/2023 7:44 PM, Abhinav Kumar wrote:
On 6/24/2023 8:03 AM, Dmitry Baryshkov wrote:
On 24/06/2023 17:17, Abhinav Kumar wrote:
On 6/24/2023 5:07 AM, Dmitry Baryshkov wrote:
On 24/06/2023 03:09, Abhinav Kumar wrote:
On 6/22/2023 5:13 PM, Dmitry Baryshkov wrote:
On 23/06/2023 02
On 6/29/2023 5:20 PM, Dmitry Baryshkov wrote:
On 29/06/2023 22:29, Abhinav Kumar wrote:
Instead of using a feature bit to decide whether to enable data
compress or not for DSC use-cases, use dpu core's major version instead.
This will avoid defining feature bits for every bit level de
On 6/29/2023 5:13 PM, Dmitry Baryshkov wrote:
On 29/06/2023 22:29, Abhinav Kumar wrote:
With [1] dpu core revision was dropped in favor of using the
compatible string from the device tree to select the dpu catalog
being used in the device.
This approach works well however also necessitates
On 6/29/2023 5:24 PM, Dmitry Baryshkov wrote:
On 29/06/2023 22:29, Abhinav Kumar wrote:
With [1] dpu core revision was dropped in favor of using the
compatible string from the device tree to select the dpu catalog
being used in the device.
This approach works well however also necessitates
On 6/29/2023 8:22 PM, Dmitry Baryshkov wrote:
On 30/06/2023 06:07, Abhinav Kumar wrote:
On 6/29/2023 5:20 PM, Dmitry Baryshkov wrote:
On 29/06/2023 22:29, Abhinav Kumar wrote:
Instead of using a feature bit to decide whether to enable data
compress or not for DSC use-cases, use dpu
Baryshkov
---
Reviewed-by: Abhinav Kumar
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
For each LM there is at max 1 peer LM which can be driven by the same
CTL, so there no need to have a mask instead of just an ID of the peer
LM.
The change is ok but the wording seems incorrect. Are you implying that
only LM0 and LM1 can be use
On 7/2/2023 6:36 PM, Dmitry Baryshkov wrote:
On Mon, 3 Jul 2023 at 04:34, Abhinav Kumar wrote:
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
For each LM there is at max 1 peer LM which can be driven by the same
CTL, so there no need to have a mask instead of just an ID of the peer
LM
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
There is always a single MDP TOP block. Drop the mdp_count field and
stop declaring dpu_mdp_cfg instances as arrays.
Tested-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
The change drops mdp_count and stops using the array which is fi
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
Since there is always just a single MDP_TOP instance, drop the enum
dpu_mdp and corresponding index value.
Reviewed-by: Marijn Suijten
Tested-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
Reviewed-by: Abhinav Kumar
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
Use more standard initialisation for .clk_ctrls definitions. Define a
single .clk_ctrls field and use array init inside.
Reviewed-by: Marijn Suijten
Tested-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
Reviewed-by: Abhinav Kumar
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
Drop useless zero assignments to the dpu_mdp_cfg::features field.
Reviewed-by: Marijn Suijten
Tested-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
Reviewed-by: Abhinav Kumar
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
Drop useless zero assignments to the dpu_ctl_cfg::features field.
Reviewed-by: Marijn Suijten
Tested-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
Reviewed-by: Abhinav Kumar
Signed-off-by: Dmitry Baryshkov
---
Reviewed-by: Abhinav Kumar
checked a few of the entries to make sure there are no copy-paste
errors but not all of them.
I am going to rely on Marijn's checksum method results that there were
no differences in the checksum and go ahead with my,
Reviewed-by: Abhinav Kumar
---
Reviewed-by: Abhinav Kumar
comment as the other change, I have cross-checked most of the
entries to make sure they match the pre-inlining values.
For the rest, I am going to rely on Marijn's checksum method.
Hence,
Reviewed-by: Abhinav Kumar
On 6/27/2023 1:29 AM, Marijn Suijten wrote:
On 2023-06-20 00:25:13, Dmitry Baryshkov wrote:
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
Tested-by: Marijn Suijten
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and visible in the source files.
Tested-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
the valu
On 7/3/2023 1:58 PM, Dmitry Baryshkov wrote:
On Mon, 3 Jul 2023 at 23:29, Abhinav Kumar wrote:
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
To simplify making changes to the hardware block definitions, expand
corresponding macros. This way making all the changes are more obvious
and
---
Reviewed-by: Abhinav Kumar
---
Reviewed-by: Abhinav Kumar
---
Reviewed-by: Abhinav Kumar
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
The MERGE_3D_SM8150_MASK features mask is zero. Drop it completely.
Reviewed-by: Marijn Suijten
Tested-by: Marijn Suijten
Signed-off-by: Dmitry Baryshkov
---
Reviewed-by: Abhinav Kumar
/disp/dpu1/catalog/dpu_4_0_sdm845.h | 4
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 2 --
3 files changed, 10 deletions(-)
Reviewed-by: Abhinav Kumar
unused, hence
Reviewed-by: Abhinav Kumar
Since its just dropping unused enum, will see if I can combine with some
other more critical fixes into a MR but not one on its own.
On 6/19/2023 5:08 PM, Dmitry Baryshkov wrote:
DPU performance module contains code to change performance state
calculations. In addition to normal (sum plane and CRTC requirements),
it can work in 'minimal' or 'fixed' modes. Both modes are impractical,
since they can easily end up with the dis
On 6/19/2023 5:08 PM, Dmitry Baryshkov wrote:
The max_per_pipe_ib is a constant across all CRTCs and is read from the
catalog. Drop corresponding calculations and read the value directly at
icc_set_bw() time.
Suggested-by: Konrad Dybcio
Signed-off-by: Dmitry Baryshkov
---
This will need t
the checks were like this due to checkpatch's earlier
limit being 80 chars.
With that relaxed, this should be fine. Hence,
Reviewed-by: Abhinav Kumar
I am unable to apply this in my branch for some reason but, hope this
doesnt break checkpatch now :)
On 7/3/2023 3:20 PM, Dmitry Baryshkov wrote:
On Tue, 4 Jul 2023 at 00:40, Abhinav Kumar wrote:
On 6/19/2023 5:08 PM, Dmitry Baryshkov wrote:
DPU performance module contains code to change performance state
calculations. In addition to normal (sum plane and CRTC requirements),
it can
On 6/19/2023 5:08 PM, Dmitry Baryshkov wrote:
The stop_req is true only in the dpu_crtc_disable() case, when
crtc->enable has already been set to false. This renders the stop_req
argument useless. Remove it completely.
What about the enable case?
That time dpu_crtc->enabled will be false
On 7/3/2023 3:53 PM, Dmitry Baryshkov wrote:
On Tue, 4 Jul 2023 at 01:37, Abhinav Kumar wrote:
On 6/19/2023 5:08 PM, Dmitry Baryshkov wrote:
The stop_req is true only in the dpu_crtc_disable() case, when
crtc->enable has already been set to false. This renders the stop_req
argum
On 6/19/2023 5:08 PM, Dmitry Baryshkov wrote:
This function does nothing, just clears several data pointers. Drop it
now.
This will undo what dpu_core_perf_init() did when an error happens.
Why can we drop that?
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_cor
On 7/3/2023 4:01 PM, Dmitry Baryshkov wrote:
On Tue, 4 Jul 2023 at 01:55, Abhinav Kumar wrote:
On 7/3/2023 3:53 PM, Dmitry Baryshkov wrote:
On Tue, 4 Jul 2023 at 01:37, Abhinav Kumar wrote:
On 6/19/2023 5:08 PM, Dmitry Baryshkov wrote:
The stop_req is true only in the
On 7/3/2023 3:59 PM, Dmitry Baryshkov wrote:
On Tue, 4 Jul 2023 at 01:57, Abhinav Kumar wrote:
On 6/19/2023 5:08 PM, Dmitry Baryshkov wrote:
This function does nothing, just clears several data pointers. Drop it
now.
This will undo what dpu_core_perf_init() did when an error happens
On 6/19/2023 5:08 PM, Dmitry Baryshkov wrote:
Remove dpu_core_perf::dev and dpu_core_perf::debugfs_root fields, they
are not used by the code.
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c | 2 --
drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.h | 4
On 7/3/2023 5:28 PM, Dmitry Baryshkov wrote:
On Tue, 4 Jul 2023 at 02:16, Abhinav Kumar wrote:
On 7/3/2023 4:01 PM, Dmitry Baryshkov wrote:
On Tue, 4 Jul 2023 at 01:55, Abhinav Kumar wrote:
On 7/3/2023 3:53 PM, Dmitry Baryshkov wrote:
On Tue, 4 Jul 2023 at 01:37, Abhinav Kumar
On 6/20/2023 4:31 AM, Konrad Dybcio wrote:
On 20.06.2023 13:18, Dmitry Baryshkov wrote:
On 20/06/2023 13:55, Konrad Dybcio wrote:
On 20.06.2023 02:08, Dmitry Baryshkov wrote:
Simplify dpu_core_perf code by using only dpu_perf_cfg instead of using
full-featured catalog data.
Signed-off-by:
On 7/3/2023 7:20 PM, Dmitry Baryshkov wrote:
On 03/07/2023 05:01, Abhinav Kumar wrote:
On 6/19/2023 2:25 PM, Dmitry Baryshkov wrote:
There is always a single MDP TOP block. Drop the mdp_count field and
stop declaring dpu_mdp_cfg instances as arrays.
Tested-by: Marijn Suijten
Signed-off
On 5/7/2023 7:15 PM, Bjorn Andersson wrote:
On Mon, May 08, 2023 at 01:06:13AM +, Leonard Lausen wrote:
This reverts commit e17af1c9d861dc177e5b56009bd4f71ace688d97.
Removing the delay of 100 units broke hot plug detection for USB-C displays on
qcom sc7180 lazor devices. Lazor uses mdss
On 5/3/2023 1:26 AM, Dmitry Baryshkov wrote:
On 03/05/2023 04:19, Jessica Zhang wrote:
Currently, word count is calculated using slice_count. This is incorrect
as downstream uses slice per packet, which is different from
slice_count.
Slice count represents the number of soft slices per inter
On 5/8/2023 4:08 PM, Dmitry Baryshkov wrote:
On 09/05/2023 00:46, Jessica Zhang wrote:
On 5/7/2023 9:00 AM, Marijn Suijten wrote:
On 2023-05-05 14:23:50, Jessica Zhang wrote:
Add DATA_COMPRESS feature flag to DPU INTF block.
In DPU 7.x and later, DSC/DCE enablement registers have been mo
On 5/8/2023 4:27 PM, Dmitry Baryshkov wrote:
On 08/05/2023 23:09, Abhinav Kumar wrote:
On 5/3/2023 1:26 AM, Dmitry Baryshkov wrote:
On 03/05/2023 04:19, Jessica Zhang wrote:
Currently, word count is calculated using slice_count. This is
incorrect
as downstream uses slice per packet
On 5/8/2023 5:47 PM, Dmitry Baryshkov wrote:
On 09/05/2023 03:45, Abhinav Kumar wrote:
On 5/8/2023 4:27 PM, Dmitry Baryshkov wrote:
On 08/05/2023 23:09, Abhinav Kumar wrote:
On 5/3/2023 1:26 AM, Dmitry Baryshkov wrote:
On 03/05/2023 04:19, Jessica Zhang wrote:
Currently, word count is
On 5/9/2023 4:42 AM, Dmitry Baryshkov wrote:
On 09/05/2023 11:54, Konrad Dybcio wrote:
On 9.05.2023 10:23, Neil Armstrong wrote:
On 09/05/2023 01:27, Dmitry Baryshkov wrote:
On 08/05/2023 23:09, Abhinav Kumar wrote:
On 5/3/2023 1:26 AM, Dmitry Baryshkov wrote:
On 03/05/2023 04:19
On 5/8/2023 4:30 AM, Dmitry Baryshkov wrote:
On 08/05/2023 14:02, Leonard Lausen wrote:
Abhinav Kumar writes:
On 5/7/2023 7:15 PM, Bjorn Andersson wrote:
When booting with the cable connected on my X13s, 100 is long enough
for
my display to time out and require me to disconnect and
On 5/10/2023 3:46 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2023-05-10 13:31:05)
Intrenal_hpd is referenced by event thread but set by drm bridge callback
context. Add mutex to protect internal_hpd to avoid conflicts between
threads.
Signed-off-by: Kuogee Hsieh
---
This patch looks co
Hi Stephen
On 5/10/2023 4:19 PM, Kuogee Hsieh wrote:
internal_hpd is referenced at both plug and unplug handle.
The majority purpose of mutext is try to serialize internal_hpd between
dp_bridge_hpd_disable() and either plug or unplug handle.
On 5/10/2023 4:11 PM, Abhinav Kumar wrote
On 5/10/2023 4:55 PM, Stephen Boyd wrote:
Quoting Kuogee Hsieh (2023-05-10 13:31:04)
The internal_hpd flag was introduced to handle external DP HPD derived from GPIO
pinmuxed into DP controller.
Was it? It looks more like it was done to differentiate between eDP and
DP, because internal_hpd
On 5/10/2023 9:29 PM, Dmitry Baryshkov wrote:
On 11/05/2023 01:07, Kuogee Hsieh wrote:
DPU < 7.0.0 requires the PINGPONG block to be involved during
DSC setting up. Since DPU >= 7.0.0, enabling and starting the DSC
encoder engine moved to INTF with the help of the flush mechanism.
Nit: was
On 5/10/2023 9:39 PM, Dmitry Baryshkov wrote:
On 11/05/2023 07:38, Abhinav Kumar wrote:
On 5/10/2023 9:29 PM, Dmitry Baryshkov wrote:
On 11/05/2023 01:07, Kuogee Hsieh wrote:
DPU < 7.0.0 requires the PINGPONG block to be involved during
DSC setting up. Since DPU >= 7.0.0, enabli
On 5/10/2023 11:28 PM, Dmitry Baryshkov wrote:
On 11/05/2023 00:03, Jessica Zhang wrote:
On 5/9/2023 11:33 PM, Marijn Suijten wrote:
On 2023-05-09 15:06:50, Jessica Zhang wrote:
Introduce MSM-specific DSC helper methods, as some calculations are
common between DP and DSC.
Reviewed-by: Dm
On 5/10/2023 11:15 PM, Marijn Suijten wrote:
On 2023-05-10 14:03:14, Jessica Zhang wrote:
On 5/9/2023 11:33 PM, Marijn Suijten wrote:
On 2023-05-09 15:06:50, Jessica Zhang wrote:
Introduce MSM-specific DSC helper methods, as some calculations are
common between DP and DSC.
Reviewed-by: D
On 5/12/2023 11:21 AM, Dmitry Baryshkov wrote:
On 12/05/2023 21:00, Kuogee Hsieh wrote:
Current DSC flush update is piggyback inside dpu_hw_ctl_intf_cfg_v1().
This patch separates DSC flush away from dpu_hw_ctl_intf_cfg_v1() by
adding dpu_hw_ctl_update_pending_flush_dsc_v1() to handle both pe
On 5/12/2023 11:50 AM, Dmitry Baryshkov wrote:
On 12/05/2023 21:47, Abhinav Kumar wrote:
On 5/12/2023 11:21 AM, Dmitry Baryshkov wrote:
On 12/05/2023 21:00, Kuogee Hsieh wrote:
Current DSC flush update is piggyback inside dpu_hw_ctl_intf_cfg_v1().
This patch separates DSC flush away from
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
Take into account the plane rotation and flipping when calculating src
positions for the wide plane parts.
Signed-off-by: Dmitry Baryshkov
Do we need to have a fixes tag for this? This means we dont consider
rotation while calculating src posi
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
As the debugfs is fully cleared on drm device removal, drop the
encoder-specific cleanup function, remove debugfs_root from dpu_encoder
struct and also remove phys_encoder late_register() ops which has been
unused since the driver being added.
A
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
The struct dpu_rm_requirements was used to wrap display topology and
hw resources, which meant INTF indices. As of commit ef58e0ad3436
("drm/msm/dpu: get INTF blocks directly rather than through RM") the hw
resources struct was removed, leaving str
8998 and SC8180X in the
title.
On 2023-05-12 11:00:16, Kuogee Hsieh wrote:
From: Abhinav Kumar
There are some platforms has DSC blocks but it is not declared at catalog.
Some platforms have DSC blocks which have not yet been declared in the
catalog.*
For completeness, this patch adds DSC bl
On 5/14/2023 10:01 AM, Dmitry Baryshkov wrote:
On Sat, 13 May 2023 at 01:12, Abhinav Kumar wrote:
On 3/20/2023 6:18 PM, Dmitry Baryshkov wrote:
Take into account the plane rotation and flipping when calculating src
positions for the wide plane parts.
Signed-off-by: Dmitry Baryshkov
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