On 1/25/2024 2:05 PM, Dmitry Baryshkov wrote:
On 25/01/2024 21:38, Paloma Arellano wrote:
All the components of YUV420 over DP are added. Therefore, let's mark the
connector property as true for DP connector when the DP type is not eDP
and when VSC SDP is supported.
Signed-off-by: Paloma Are
On 1/28/2024 7:23 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 05:06, Abhinav Kumar wrote:
On 1/26/2024 4:39 PM, Paloma Arellano wrote:
On 1/25/2024 1:14 PM, Dmitry Baryshkov wrote:
On 25/01/2024 21:38, Paloma Arellano wrote:
Generalize dpu_encoder_helper_phys_setup_cdm to be
On 1/28/2024 7:52 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 05:17, Abhinav Kumar wrote:
On 1/25/2024 2:05 PM, Dmitry Baryshkov wrote:
On 25/01/2024 21:38, Paloma Arellano wrote:
All the components of YUV420 over DP are added. Therefore, let's mark the
connector proper
On 1/28/2024 8:12 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 06:01, Abhinav Kumar wrote:
On 1/28/2024 7:23 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 05:06, Abhinav Kumar wrote:
On 1/26/2024 4:39 PM, Paloma Arellano wrote:
On 1/25/2024 1:14 PM, Dmitry Baryshkov
On 1/28/2024 7:42 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 04:58, Abhinav Kumar wrote:
On 1/27/2024 9:55 PM, Dmitry Baryshkov wrote:
On Sun, 28 Jan 2024 at 07:48, Paloma Arellano wrote:
On 1/25/2024 1:57 PM, Dmitry Baryshkov wrote:
On 25/01/2024 21:38, Paloma Arellano
On 1/28/2024 9:05 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 06:30, Abhinav Kumar wrote:
On 1/28/2024 7:52 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 05:17, Abhinav Kumar wrote:
On 1/25/2024 2:05 PM, Dmitry Baryshkov wrote:
On 25/01/2024 21:38, Paloma Arellano
On 1/28/2024 10:12 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 07:03, Abhinav Kumar wrote:
On 1/28/2024 7:42 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 04:58, Abhinav Kumar wrote:
On 1/27/2024 9:55 PM, Dmitry Baryshkov wrote:
On Sun, 28 Jan 2024 at 07:48, Paloma
Hi Maxime
On 1/26/2024 4:45 AM, Maxime Ripard wrote:
On Wed, Jan 17, 2024 at 09:36:20AM -0800, Abhinav Kumar wrote:
Hi Jani and Maxime
On 1/17/2024 2:16 AM, Jani Nikula wrote:
On Wed, 17 Jan 2024, Maxime Ripard wrote:
Hi,
On Tue, Jan 16, 2024 at 02:22:03PM -0800, Jessica Zhang wrote
On 1/27/2024 9:33 PM, Dmitry Baryshkov wrote:
On Sun, 28 Jan 2024 at 07:16, Paloma Arellano wrote:
On 1/25/2024 1:26 PM, Dmitry Baryshkov wrote:
On 25/01/2024 21:38, Paloma Arellano wrote:
INTF_CONFIG2 register cannot have widebus enabled when DP format is
YUV420. Therefore, program the
On 1/29/2024 4:03 PM, Dmitry Baryshkov wrote:
On Tue, 30 Jan 2024 at 01:51, Abhinav Kumar wrote:
On 1/27/2024 9:33 PM, Dmitry Baryshkov wrote:
On Sun, 28 Jan 2024 at 07:16, Paloma Arellano wrote:
On 1/25/2024 1:26 PM, Dmitry Baryshkov wrote:
On 25/01/2024 21:38, Paloma Arellano
On 1/29/2024 5:43 PM, Dmitry Baryshkov wrote:
On Tue, 30 Jan 2024 at 03:07, Abhinav Kumar wrote:
On 1/29/2024 4:03 PM, Dmitry Baryshkov wrote:
On Tue, 30 Jan 2024 at 01:51, Abhinav Kumar wrote:
On 1/27/2024 9:33 PM, Dmitry Baryshkov wrote:
On Sun, 28 Jan 2024 at 07:16, Paloma
On 1/29/2024 9:28 PM, Dmitry Baryshkov wrote:
On Tue, 30 Jan 2024 at 06:10, Abhinav Kumar wrote:
On 1/29/2024 5:43 PM, Dmitry Baryshkov wrote:
On Tue, 30 Jan 2024 at 03:07, Abhinav Kumar wrote:
On 1/29/2024 4:03 PM, Dmitry Baryshkov wrote:
On Tue, 30 Jan 2024 at 01:51, Abhinav
enabling
INTF_CFG2_DATA_HCTL_EN for all other cases when supported by DPU.
Fixes: 3309a7563971 ("drm/msm/dpu: revise timing engine programming to support
widebus feature")
Suggested-by: Dmitry Baryshkov
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
On 1/31/2024 5:05 PM, Dmitry Baryshkov wrote:
On Thu, 1 Feb 2024 at 02:48, Abhinav Kumar wrote:
Currently INTF_CFG2_DATA_HCTL_EN is coupled with the enablement
of widebus but this is incorrect because we should be enabling
this bit independent of widebus except for cases where compression
On 1/29/2024 3:44 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 09:08, Abhinav Kumar wrote:
On 1/28/2024 10:12 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 07:03, Abhinav Kumar wrote:
On 1/28/2024 7:42 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 04:58, Abhinav
On 1/27/2024 9:39 PM, Dmitry Baryshkov wrote:
On Sun, 28 Jan 2024 at 07:34, Paloma Arellano wrote:
On 1/25/2024 1:48 PM, Dmitry Baryshkov wrote:
On 25/01/2024 21:38, Paloma Arellano wrote:
Add support to pack and send the VSC SDP packet for DP. This therefore
allows the transmision of fo
On 1/31/2024 7:17 PM, Dmitry Baryshkov wrote:
On Thu, 1 Feb 2024 at 03:30, Abhinav Kumar wrote:
On 1/29/2024 3:44 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 09:08, Abhinav Kumar wrote:
On 1/28/2024 10:12 PM, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 07:03, Abhinav Kumar
On 1/31/2024 8:36 PM, Dmitry Baryshkov wrote:
On Thu, 1 Feb 2024 at 03:56, Abhinav Kumar wrote:
On 1/27/2024 9:39 PM, Dmitry Baryshkov wrote:
On Sun, 28 Jan 2024 at 07:34, Paloma Arellano wrote:
On 1/25/2024 1:48 PM, Dmitry Baryshkov wrote:
On 25/01/2024 21:38, Paloma Arellano
pping up to maintain this
Reviewed-by: Abhinav Kumar
---
.../devicetree/bindings/display/bridge/ti,sn65dsi86.yaml| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml
b/Documentation/devicetree/bindings/di
On 10/5/2023 3:06 PM, Dmitry Baryshkov wrote:
The frame event callback is always set to dpu_crtc_frame_event_cb() (or
to NULL) and the data is always either the CRTC itself or NULL
(correpondingly). Thus drop the event callback registration, call the
dpu_crtc_frame_event_cb() directly and gate
On 1/5/2024 3:34 PM, Dmitry Baryshkov wrote:
Older (mdp5) platforms do not use per-SoC compatible strings. Instead
they use a single compat entry 'qcom,mdss'. To facilitate migrating
these platforms to the DPU driver provide a way to generate the MDSS /
UBWC data at runtime, when the DPU drive
On 1/5/2024 3:34 PM, Dmitry Baryshkov wrote:
Existing MDP5 devices have slightly different bindings. The main
register region is called `mdp_phys' instead of `mdp'. Also vbif
register regions are a part of the parent, MDSS device. Add support for
handling this binding differences.
Signed-off-
platforms supported by both drivers are by default handled by the
MDP5 driver. To let them be handled by the DPU driver pass the
`msm.prefer_mdp5=false` kernel param.
Reviewed-by: Stephen Boyd
Signed-off-by: Dmitry Baryshkov
---
Reviewed-by: Abhinav Kumar
s but certainly
not all, but based on whatever I checked all the entries were correct in
the catalog.
Reviewed-by: Abhinav Kumar
On 2/7/2024 11:56 AM, Dmitry Baryshkov wrote:
On Wed, 7 Feb 2024 at 20:48, Abhinav Kumar wrote:
On 1/5/2024 3:34 PM, Dmitry Baryshkov wrote:
Existing MDP5 devices have slightly different bindings. The main
register region is called `mdp_phys' instead of `mdp'. Also vbif
regist
On 2/8/2024 5:46 AM, Abel Vesa wrote:
On 24-02-08 15:42:04, Dmitry Baryshkov wrote:
On Thu, 8 Feb 2024 at 15:37, Abel Vesa wrote:
On 24-01-29 17:11:25, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 15:19, Abel Vesa wrote:
Add support for MDSS on X1E80100.
Signed-off-by: Abel Vesa
--
msm/dsi/dsi_host.c | 33 +++--
1 file changed, 31 insertions(+), 2 deletions(-)
Reviewed-by: Abhinav Kumar
hanged, 68 insertions(+), 59 deletions(-)
+
+ crtc = conn_state->crtc;
+ if (!crtc)
+ return 0;
+
This should fix the crash and rest of the change LGTM
Reviewed-by: Abhinav Kumar
Please give us a couple of days to re-test this and give our Tested-by
as we plan
dss.c | 51 ++
1 file changed, 51 insertions(+)
Reviewed-by: Abhinav Kumar
on a quite version of msm_ioremap_mdss for
vbif_nrt_phys?
Anyway, its not something to block this change. Hence,
Reviewed-by: Abhinav Kumar
changed, 8 insertions(+)
Reviewed-by: Abhinav Kumar
ned-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 -
2 files changed, 9 deletions(-)
Reviewed-by: Abhinav Kumar
files changed, 15 insertions(+), 49 deletions(-)
Nice cleanup !
Reviewed-by: Abhinav Kumar
ned-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 8
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h | 1 -
2 files changed, 9 deletions(-)
Reviewed-by: Abhinav Kumar
On 2/10/2024 2:09 AM, Dmitry Baryshkov wrote:
On Sat, 10 Feb 2024 at 03:52, Paloma Arellano wrote:
Add support to pack and send the VSC SDP packet for DP. This therefore
allows the transmision of format information to the sinks which is
needed for YUV420 support over DP.
Changes in v2:
On 2/10/2024 10:14 AM, Abhinav Kumar wrote:
On 2/10/2024 2:09 AM, Dmitry Baryshkov wrote:
On Sat, 10 Feb 2024 at 03:52, Paloma Arellano
wrote:
Add support to pack and send the VSC SDP packet for DP. This therefore
allows the transmision of format information to the sinks which is
needed
On 2/10/2024 3:33 AM, Dmitry Baryshkov wrote:
On Sat, 10 Feb 2024 at 03:52, Paloma Arellano wrote:
All the components of YUV420 over DP are added. Therefore, let's mark the
connector property as true for DP connector when the DP type is not eDP
and when there is a CDM block available.
Chan
: Paloma Arellano
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/display/drm_dp_helper.c | 21 +
include/drm/display/drm_dp_helper.h | 1 +
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_helper.c
b/drivers/gpu/drm/display/drm_dp_helper.c
On 2/10/2024 2:16 AM, Dmitry Baryshkov wrote:
On Sat, 10 Feb 2024 at 03:52, Paloma Arellano wrote:
DP controller can be setup to operate in either SDP update flush mode or
peripheral flush mode based on the DP controller hardware version.
Starting in DP v1.2, the hardware documents require
On 2/10/2024 1:46 PM, Dmitry Baryshkov wrote:
On Sat, 10 Feb 2024 at 20:50, Abhinav Kumar wrote:
On 2/10/2024 10:14 AM, Abhinav Kumar wrote:
On 2/10/2024 2:09 AM, Dmitry Baryshkov wrote:
On Sat, 10 Feb 2024 at 03:52, Paloma Arellano
wrote:
Add support to pack and send the VSC SDP
On 2/10/2024 2:11 PM, Dmitry Baryshkov wrote:
On Sat, 10 Feb 2024 at 23:49, Abhinav Kumar wrote:
On 2/10/2024 2:16 AM, Dmitry Baryshkov wrote:
On Sat, 10 Feb 2024 at 03:52, Paloma Arellano wrote:
DP controller can be setup to operate in either SDP update flush mode or
peripheral
On 2/10/2024 10:57 PM, Dmitry Baryshkov wrote:
On Sun, 11 Feb 2024 at 06:06, Abhinav Kumar wrote:
On 2/10/2024 1:46 PM, Dmitry Baryshkov wrote:
On Sat, 10 Feb 2024 at 20:50, Abhinav Kumar wrote:
On 2/10/2024 10:14 AM, Abhinav Kumar wrote:
On 2/10/2024 2:09 AM, Dmitry Baryshkov
://patchwork.freedesktop.org/series/129180/
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Paloma Arellano
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/display/drm_dp_helper.c | 23 +++
include/drm/display/drm_dp_helper.h | 1 +
2 files changed, 24 insertions(+)
diff --git a/drivers/gpu/drm
On 2/10/2024 1:17 PM, Dmitry Baryshkov wrote:
On Sat, 10 Feb 2024 at 21:19, Abhinav Kumar wrote:
On 2/10/2024 3:33 AM, Dmitry Baryshkov wrote:
On Sat, 10 Feb 2024 at 03:52, Paloma Arellano wrote:
All the components of YUV420 over DP are added. Therefore, let's mark the
conn
rtc.c | 1 +
1 file changed, 1 insertion(+)
Nice catch !!
Reviewed-by: Abhinav Kumar
On 2/12/2024 1:20 PM, Dmitry Baryshkov wrote:
On Mon, 12 Feb 2024 at 23:13, Abhinav Kumar wrote:
On 2/10/2024 1:17 PM, Dmitry Baryshkov wrote:
On Sat, 10 Feb 2024 at 21:19, Abhinav Kumar wrote:
On 2/10/2024 3:33 AM, Dmitry Baryshkov wrote:
On Sat, 10 Feb 2024 at 03:52, Paloma
On 2/13/2024 3:18 AM, Dmitry Baryshkov wrote:
On Sat, 10 Feb 2024 at 03:53, Paloma Arellano wrote:
Adjust the encoder format programming in the case of video mode for DP
to accommodate CDM related changes.
Changes in v2:
- Move timing engine programming to a separate patch from th
Hi Johan
Thanks for the report.
I do agree that pm runtime eDP driver got merged that time but I think
the issue is either a combination of that along with DRM aux bridge
https://patchwork.freedesktop.org/series/122584/ OR just the latter as
even that went in around the same time.
Thats why
On 2/13/2024 10:23 AM, Dmitry Baryshkov wrote:
On Tue, 13 Feb 2024 at 19:32, Abhinav Kumar wrote:
On 2/13/2024 3:18 AM, Dmitry Baryshkov wrote:
On Sat, 10 Feb 2024 at 03:53, Paloma Arellano wrote:
Adjust the encoder format programming in the case of video mode for DP
to accommodate
On 2/13/2024 11:31 AM, Dmitry Baryshkov wrote:
On Tue, 13 Feb 2024 at 20:46, Abhinav Kumar wrote:
On 2/13/2024 10:23 AM, Dmitry Baryshkov wrote:
On Tue, 13 Feb 2024 at 19:32, Abhinav Kumar wrote:
On 2/13/2024 3:18 AM, Dmitry Baryshkov wrote:
On Sat, 10 Feb 2024 at 03:53, Paloma
On 2/13/2024 1:16 PM, Dmitry Baryshkov wrote:
On Tue, 13 Feb 2024 at 23:10, Abhinav Kumar wrote:
On 2/13/2024 11:31 AM, Dmitry Baryshkov wrote:
On Tue, 13 Feb 2024 at 20:46, Abhinav Kumar wrote:
On 2/13/2024 10:23 AM, Dmitry Baryshkov wrote:
On Tue, 13 Feb 2024 at 19:32, Abhinav
intel_dp_vsc_sdp_pack() can be re-used by other DRM drivers as well.
Lets move this to drm_dp_helper to achieve this.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/display/drm_dp_helper.c | 78 +
drivers/gpu/drm/i915/display/intel_dp.c | 73
On 2/14/2024 12:15 AM, Dmitry Baryshkov wrote:
On Wed, 14 Feb 2024 at 01:45, Abhinav Kumar wrote:
intel_dp_vsc_sdp_pack() can be re-used by other DRM drivers as well.
Lets move this to drm_dp_helper to achieve this.
Signed-off-by: Abhinav Kumar
My preference would be to have packing
On 2/8/2024 6:50 AM, Dmitry Baryshkov wrote:
We have several reports of vblank timeout messages. However after some
debugging it was found that there might be different causes to that.
To allow us to identify the DPU block that gets stuck, include the
actual CTL_FLUSH value into the timeout me
On 2/14/2024 10:02 AM, Ville Syrjälä wrote:
On Wed, Feb 14, 2024 at 09:17:34AM -0800, Abhinav Kumar wrote:
On 2/14/2024 12:15 AM, Dmitry Baryshkov wrote:
On Wed, 14 Feb 2024 at 01:45, Abhinav Kumar wrote:
intel_dp_vsc_sdp_pack() can be re-used by other DRM drivers as well.
Lets move
On 9/13/2023 10:06 PM, Dmitry Baryshkov wrote:
The helper drm_atomic_helper_check_plane_state() runs several checks on
plane src and dst rectangles, including the check whether required
scaling fits into the required margins. The msm driver would benefit
from having a function that does all th
On 9/13/2023 10:06 PM, Dmitry Baryshkov wrote:
Provide atomic_print_state callback to the DPU's private object. This
way the debugfs/dri/0/state will also include RM's internal state.
I like this idea !
Signed-off-by: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 4 ++
On 9/13/2023 10:06 PM, Dmitry Baryshkov wrote:
Take into account the plane rotation and flipping when calculating src
positions for the wide plane parts.
This is not an issue yet, because rotation is only supported for the
UBWC planes and wide UBWC planes are rejected anyway because in parall
On 2/14/2024 11:39 AM, Dmitry Baryshkov wrote:
On Wed, 14 Feb 2024 at 20:04, Paloma Arellano wrote:
Add support to pack and send the VSC SDP packet for DP. This therefore
allows the transmision of format information to the sinks which is
needed for YUV420 support over DP.
Changes in v3:
On 2/14/2024 11:20 AM, Dmitry Baryshkov wrote:
On Wed, 14 Feb 2024 at 20:02, Abhinav Kumar wrote:
On 2/8/2024 6:50 AM, Dmitry Baryshkov wrote:
We have several reports of vblank timeout messages. However after some
debugging it was found that there might be different causes to that.
To
On 2/15/2024 12:45 AM, Dmitry Baryshkov wrote:
On Wed, 14 Feb 2024 at 20:04, Paloma Arellano wrote:
Adjust the encoder format programming in the case of video mode for DP
to accommodate CDM related changes.
Changes in v2:
- Move timing engine programming to a separate patch from t
On 2/15/2024 12:40 AM, Dmitry Baryshkov wrote:
On Wed, 14 Feb 2024 at 22:15, Abhinav Kumar wrote:
On 2/14/2024 11:39 AM, Dmitry Baryshkov wrote:
On Wed, 14 Feb 2024 at 20:04, Paloma Arellano wrote:
Add support to pack and send the VSC SDP packet for DP. This therefore
allows the
intel_dp_vsc_sdp_pack() can be re-used by other DRM drivers as well.
Lets move this to drm_dp_helper to achieve this.
changes in v2:
- rebased on top of drm-tip
Acked-by: Dmitry Baryshkov
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/display/drm_dp_helper.c | 78
drm_dp_helper.c
[1]: https://patchwork.freedesktop.org/series/129180/
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Paloma Arellano
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/display/drm_dp_helper.c | 23 +++
include/drm/display/drm_dp_helper.h | 2 ++
2 files
On 5/8/2024 2:17 AM, Jon Hunter wrote:
Building the kernel with python3 versions earlier than v3.9 fails with ...
Traceback (most recent call last):
File "drivers/gpu/drm/msm/registers/gen_header.py", line 970, in
main()
File "drivers/gpu/drm/msm/registers/gen_header.py", lin
On 5/8/2024 1:43 AM, Jani Nikula wrote:
On Tue, 07 May 2024, Abhinav Kumar wrote:
Since commit 5acf49119630 ("drm/msm: import gen_header.py script from Mesa"),
compilation is broken on machines having python versions older than 3.9
due to dependency on argparse.BooleanOptionalAc
On 5/8/2024 3:41 PM, Doug Anderson wrote:
Hi,
On Fri, May 3, 2024 at 11:15 AM Dmitry Baryshkov
wrote:
@@ -941,6 +948,7 @@ def main():
parser = argparse.ArgumentParser()
parser.add_argument('--rnn', type=str, required=True)
parser.add_argument('--xml', type=str, r
== ===
Is it really optional - can you build the driver without it?
True, we cannot build the driver now without it. So we should be
dropping the optional tag.
With that addressed,
Reviewed-by: Abhinav Kumar
This
On 5/9/2024 10:52 AM, Barnabás Czémán wrote:
CTLs on older qualcomm SOCs like msm8953 and msm8996 has not got interrupts,
so better to skip CTL irq callback register/unregister
make dpu_ctl_cfg be able to define without intr_start.
Thanks for the patch.
Have msm8953 and msm8996 migrated to
/drm/msm/disp/dpu1/dpu_encoder.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
I think we also need
Fixes: 5a9d50150c2c ("drm/msm/dpu: shift IRQ indices by 1")
With that,
Reviewed-by: Abhinav Kumar
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/dr
functional change, so you could have retained by R-b, but here it is
again,
Reviewed-by: Abhinav Kumar
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 119f3ea50a7c..cf7d769ab3b9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encod
(+)
Reviewed-by: Abhinav Kumar
On 5/14/2024 12:56 AM, Dmitry Baryshkov wrote:
In the DPU driver blank IRQ handling is called from a vblank worker and
can happen outside of the irq_enable / irq_disable pair. Revert commit
d13f638c9b88 ("drm/msm/dpu: drop dpu_encoder_phys_ops.atomic_mode_set")
to fix vblank IRQ assignment for
To debug display mmu faults, this series introduces a display fault
handler similar to the gpu one.
This is only compile tested at the moment, till a suitable method
to trigger the fault is found and see if this handler does the needful
on the device.
Abhinav Kumar (4):
drm/msm: register a
Switch msm_kms to use msm_iommu_disp_new() so that the newly
registered fault handler will kick-in during any mmu faults.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/msm_kms.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers
Introduce a new API msm_iommu_disp_new() for display use-cases.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/msm_iommu.c | 28
drivers/gpu/drm/msm/msm_mmu.h | 1 +
2 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers
In preparation of registering a separate fault handler for
display, lets rename the existing msm_fault_handler to
msm_gpu_fault_handler.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/msm_iommu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm
faults.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/msm_kms.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c
index af6a6fcb1173..62c8e6163e81 100644
--- a/drivers/gpu/drm/msm/msm_kms.c
+++ b
On 5/20/2024 5:12 AM, Dmitry Baryshkov wrote:
Command mode panels provide TE signal back to the DSI host to signal
that the frame display has completed and update of the image will not
cause tearing. Usually it is connected to the first GPIO with the
mdp_vsync function, which is the default. I
On 5/20/2024 5:12 AM, Dmitry Baryshkov wrote:
Command-mode DSI panels need to signal the display controlller when
vsync happens, so that the device can start sending the next frame. Some
devices (Google Pixel 3) use a non-default pin, so additional
configuration is required. Add a way to speci
OURCE_WD_TIMER_015
+enum dpu_vsync_source {
+ DPU_VSYNC_SOURCE_GPIO_0,
+ DPU_VSYNC_SOURCE_GPIO_1,
+ DPU_VSYNC_SOURCE_GPIO_2,
+ DPU_VSYNC_SOURCE_INTF_0 = 3,
Do we need this assignment to 3?
Rest LGTM,
Reviewed-by: Abhinav Kumar
-
1 file changed, 37 deletions(-)
Reviewed-by: Abhinav Kumar
/dpu_encoder.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Abhinav Kumar
: Dmitry Baryshkov
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 5 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 5 ++---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++
3 files changed, 5 insertions(+), 7 deletions(-)
Reviewed-by: Abhinav Kumar
On 5/22/2024 1:05 PM, Dmitry Baryshkov wrote:
On Wed, 22 May 2024 at 21:38, Abhinav Kumar wrote:
On 5/20/2024 5:12 AM, Dmitry Baryshkov wrote:
Command mode panels provide TE signal back to the DSI host to signal
that the frame display has completed and update of the image will not
cause
On 5/22/2024 1:01 PM, Dmitry Baryshkov wrote:
On Wed, 22 May 2024 at 21:41, Abhinav Kumar wrote:
On 5/20/2024 5:12 AM, Dmitry Baryshkov wrote:
Add enum dpu_vsync_source instead of a series of defines. Use this enum
to pass vsync information.
Signed-off-by: Dmitry Baryshkov
wb2_format arrays
for rgb and yuv")
Fixes: 53324b99bd7b ("drm/msm/dpu: add writeback blocks to the sm8250
DPU catalog")
Reviewed-by: Abhinav Kumar
(pls ignore the line breaks in the fixes line, I will fix it while applying)
Hello
On 5/24/2024 12:55 PM, Paul E. McKenney wrote:
Hello!
I get the following allmodconfig build error on x86 in next-20240523:
Traceback (most recent call last):
File "drivers/gpu/drm/msm/registers/gen_header.py", line 970, in
main()
File "drivers/gpu/drm/msm/registers/gen_heade
On 5/22/2024 3:24 AM, Dmitry Baryshkov wrote:
In the DPU driver blank IRQ handling is called from a vblank worker and
can happen outside of the irq_enable / irq_disable pair. Using the
worker makes that completely asynchronous with the rest of the code.
Revert commit d13f638c9b88 ("drm/msm/dpu
On 5/29/2024 2:48 AM, Vignesh Raman wrote:
Hi Dmitry,
On 29/05/24 13:39, Dmitry Baryshkov wrote:
On Wed, May 29, 2024 at 08:10:47AM +0530, Vignesh Raman wrote:
test-list.txt and test-list-full.txt are not generated for
cross-builds and they are required by drm-ci for testing
arm32 targets.
On 5/23/2024 2:58 AM, Dmitry Baryshkov wrote:
On Thu, 23 May 2024 at 02:57, Abhinav Kumar wrote:
On 5/22/2024 1:05 PM, Dmitry Baryshkov wrote:
On Wed, 22 May 2024 at 21:38, Abhinav Kumar wrote:
On 5/20/2024 5:12 AM, Dmitry Baryshkov wrote:
Command mode panels provide TE signal
| 1 +
drivers/gpu/drm/msm/dsi/dsi_host.c| 11 +++
drivers/gpu/drm/msm/dsi/dsi_manager.c | 5 +
drivers/gpu/drm/msm/msm_drv.h | 6 ++
4 files changed, 23 insertions(+)
Reviewed-by: Abhinav Kumar
On 5/22/2024 12:59 PM, Dmitry Baryshkov wrote:
On Wed, 22 May 2024 at 21:39, Abhinav Kumar wrote:
On 5/20/2024 5:12 AM, Dmitry Baryshkov wrote:
Command-mode DSI panels need to signal the display controlller when
vsync happens, so that the device can start sending the next frame. Some
On 5/24/2024 1:22 PM, Dmitry Baryshkov wrote:
On Fri, May 24, 2024 at 12:58:53PM -0700, Abhinav Kumar wrote:
On 5/22/2024 3:24 AM, Dmitry Baryshkov wrote:
In the DPU driver blank IRQ handling is called from a vblank worker and
can happen outside of the irq_enable / irq_disable pair. Using
On 5/29/2024 5:02 PM, Dmitry Baryshkov wrote:
On Thu, 30 May 2024 at 00:57, Abhinav Kumar wrote:
On 5/23/2024 2:58 AM, Dmitry Baryshkov wrote:
On Thu, 23 May 2024 at 02:57, Abhinav Kumar wrote:
On 5/22/2024 1:05 PM, Dmitry Baryshkov wrote:
On Wed, 22 May 2024 at 21:38, Abhinav
rivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Good catch !
LGTM
Reviewed-by: Abhinav Kumar
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 3b1ed02f644d..89a6344bc865 100644
--- a/drive
On 11/16/2023 12:36 PM, Abhinav Kumar wrote:
On 11/9/2023 4:02 PM, Jonathan Marek wrote:
Use the same value as the downstream driver. This change is needed for
CPHY
mode to work correctly.
Fixes: 8b034e6771113 ("drm/msm/dsi: add support for DSI-PHY on SM8550")
One error her
On 11/1/2023 12:23 PM, Abhinav Kumar wrote:
On 10/13/2023 1:25 AM, Dan Carpenter wrote:
This NULL check was required when it was added, but we shuffled the code
around and now it's not. The inconsistent NULL checking triggers a
Smatch warning:
drivers/gpu/drm/msm/disp
change this number everytime we add a new KMS property.
Reviewed-by: Harry Wentland
Reviewed-by: Simon Ser
Signed-off-by: Melissa Wen
Reviewed-by: Abhinav Kumar
---
include/drm/drm_mode_object.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/drm
ktop.org/drm/msm/-/commit/b3e0f94d1570
Best regards,
--
Abhinav Kumar
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