On Thu, Dec 7, 2017 at 8:25 PM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> Hi,
>
> On Thu, Dec 07, 2017 at 02:05:47PM +0800, Chen-Yu Tsai wrote:
>> > +static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon,
>> > +
e the case when using the frontend and then routing its
> output to the backend.
>
> Reviewed-by: Neil Armstrong <narmstr...@baylibre.com>
> Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
___
* The array of struct drm_plane backing the layers, or an
> +* error pointer on failure.
> +*/
> struct drm_plane **(*layers_init)(struct drm_device *drm,
> struct sunxi_engine *engine);
>
> - void (*apply_color
e YUV plane or one
> plane that uses the frontend output.
>
> Let's allow our engines to provide an atomic_check callback to validate the
> current configuration.
>
> Reviewed-by: Neil Armstrong <narmstr...@baylibre.com>
> Signed-off-by: Maxime Ripard <maxime.rip...@f
lane should use the frontend.
>
> Reviewed-by: Neil Armstrong <narmstr...@baylibre.com>
> Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
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struct sunxi_engine *engine);
>
> + /**
> + * @vblank_quirk:
> +*
> +* This callback is used to implement backend-specific
^ engine
Otherwise,
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
> +* behaviour part of t
ngine.h
> +++ b/drivers/gpu/drm/sun4i/sunxi_engine.h
> @@ -33,6 +33,19 @@ struct sunxi_engine_ops {
> void (*apply_color_correction)(struct sunxi_engine *engine);
>
> /**
> +* @atomic_begin:
> +*
> +* This callback allows to prepare our backend fo
can use only the LVDS output on the first TCON. The other parts will be
> added eventually.
>
> Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
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On Tue, Dec 5, 2017 at 11:10 PM, Maxime Ripard
wrote:
> The TCON supports the LVDS interface to output to a panel or a bridge.
> Let's add support for it.
>
> Signed-off-by: Maxime Ripard
> ---
> drivers/gpu/drm/sun4i/Makefile
gt;>
>> Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
>> ---
>> Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 3 +++
>> 1 file changed, 3 insertions(+)
>
> Reviewed-by: Rob Herring <r...@kernel.org>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
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I, unlike most other PMIC
> DTSI, it obviously wasn't probing anymore.
>
> Re-add it so that everything works again.
>
> Fixes: 90c5d7cdae64 ("ARM: dts: sun8i: a711: Add regulator support")
> Signed-off-by: Maxime Ripard <maxime.rip...@free-
On Tue, Dec 5, 2017 at 11:10 PM, Maxime Ripard
wrote:
> Some clocks and resets supposed to drive the LVDS logic in the display
> engine have been overlooked when the driver was first introduced.
>
> Add those additional resources to the binding, and we'll deal
I noticed it after the patch was merged,
but then I got busy with other stuff.
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
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On Mon, May 14, 2018 at 1:20 AM, Jagan Teki <ja...@amarulasolutions.com> wrote:
> On Tue, May 1, 2018 at 9:53 PM, Chen-Yu Tsai <w...@csie.org> wrote:
>> On Mon, Apr 30, 2018 at 7:40 PM, Jagan Teki <ja...@amarulasolutions.com>
>> wrote:
>>> Allwinner 64
On Mon, May 14, 2018 at 11:03 AM, Jagan Teki <ja...@amarulasolutions.com> wrote:
> On Thu, Apr 19, 2018 at 3:02 PM, Chen-Yu Tsai <w...@csie.org> wrote:
>> This panel is marketed as Banana Pi 7" LCD display. On the back is
>> a sticker denoting the model name
On Wed, May 16, 2018 at 12:20 AM, Jagan Teki <ja...@amarulasolutions.com> wrote:
> On Wed, May 16, 2018 at 12:12 PM, Chen-Yu Tsai <w...@csie.org> wrote:
>> On Mon, May 14, 2018 at 11:03 AM, Jagan Teki <ja...@amarulasolutions.com>
>> wrote:
>>> On Thu
On Thu, May 24, 2018 at 1:50 AM, Maxime Ripard
wrote:
> On Mon, May 21, 2018 at 07:27:46PM +0200, Jernej Škrabec wrote:
>> Hi,
>>
>> Dne ponedeljek, 21. maj 2018 ob 10:07:59 CEST je Maxime Ripard napisal(a):
>> > On Sat, May 19, 2018 at 08:31:18PM +0200, Jernej Skrabec
On Sat, Jun 16, 2018 at 1:33 AM, Jernej Škrabec wrote:
> Dne petek, 15. junij 2018 ob 19:13:17 CEST je Chen-Yu Tsai napisal(a):
>> On Sat, Jun 16, 2018 at 12:41 AM, Jernej Škrabec
>>
>> wrote:
>> > Hi,
>> >
>> > Dne petek, 15. junij 2018 ob 10:
On Wed, Jun 13, 2018 at 4:00 AM, Jernej Skrabec wrote:
> Display related peripherals need precise clocks to operate correctly.
>
> Allow DE2, TCONs and HDMI to set parent clock.
>
> Signed-off-by: Jernej Skrabec
Reviewed-by: Chen-Yu Tsai
t;
> Signed-off-by: Jernej Skrabec
Reviewed-by: Chen-Yu Tsai
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On Wed, Jun 13, 2018 at 3:46 PM, Maxime Ripard
wrote:
> On Tue, Jun 12, 2018 at 10:00:23PM +0200, Jernej Skrabec wrote:
>> TV TCONs are always connected to TV or HDMI encoder, so it doesn't make
>> sense to check if panel or bridge is connected to them.
>>
>> Check if TCON has channel 0 and only
On Sat, Jun 16, 2018 at 12:41 AM, Jernej Škrabec
wrote:
> Hi,
>
> Dne petek, 15. junij 2018 ob 10:31:10 CEST je Maxime Ripard napisal(a):
>> Hi,
>>
>> On Tue, Jun 12, 2018 at 10:00:20PM +0200, Jernej Skrabec wrote:
>> > TV TCONs connected to TCON TOP have to enable additional gate in order
>> >
On Fri, Jun 1, 2018 at 8:29 AM, Maxime Ripard wrote:
> On Thu, May 31, 2018 at 07:54:08PM +0200, Jernej Škrabec wrote:
>> Dne četrtek, 31. maj 2018 ob 11:21:33 CEST je Maxime Ripard napisal(a):
>> > On Thu, May 24, 2018 at 03:01:09PM -0700, Chen-Yu Tsai wrote:
>> >
On Sun, Jul 1, 2018 at 6:41 PM, Jernej Škrabec wrote:
> Dne četrtek, 28. junij 2018 ob 08:51:07 CEST je Chen-Yu Tsai napisal(a):
>> On Thu, Jun 28, 2018 at 1:15 PM, Jernej Škrabec
> wrote:
>> > Dne četrtek, 28. junij 2018 ob 04:50:09 CEST je Chen-Yu Tsai napisal(a):
>&
On Sat, Jun 30, 2018 at 3:15 AM, Jernej Škrabec wrote:
> Dne četrtek, 28. junij 2018 ob 03:53:36 CEST je Chen-Yu Tsai napisal(a):
>> On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec
> wrote:
>> > sun4i_drv_add_endpoints() has a memory leak since it uses of_node_put()
>
On Sat, Jun 30, 2018 at 3:09 AM, Jernej Škrabec wrote:
> Dne četrtek, 28. junij 2018 ob 03:47:20 CEST je Chen-Yu Tsai napisal(a):
>> Hi,
>>
>> So I'm late to the party, but...
>>
>> On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec
> wrote:
>> >
On Sat, Jun 30, 2018 at 3:19 AM, Jernej Škrabec wrote:
> Dne četrtek, 28. junij 2018 ob 04:22:36 CEST je Chen-Yu Tsai napisal(a):
>> On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec
> wrote:
>> > Current DW HDMI PHY code never prepares and enables PHY clock after it is
&g
On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec wrote:
> Video PLLs need to be referenced in R40 DT as possible HDMI PHY parent.
>
> Export them.
>
> Reviewed-by: Rob Herring
> Signed-off-by: Jernej Skrabec
Reviewed-by: Chen-Yu Tsai
___
Hi,
So I'm late to the party, but...
On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec wrote:
> As already described in DT binding, TCON TOP is responsible for
> configuring display pipeline. In this initial driver focus is on HDMI
> pipeline, so TVE and LCD configuration is not implemented.
>
>
On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec wrote:
> TV TCONs (channel 1 only) are always connected to TV or HDMI encoder.
> Because of that, all output endpoints on such TCON node will point to a
> encoder which is part of component framework.
>
> Correct current graph traversing algorithm
On Mon, Jun 25, 2018 at 8:02 PM, Jernej Skrabec wrote:
> sun4i_drv_add_endpoints() has a memory leak since it uses of_node_put()
> when remote is equal to NULL and does nothing when remote has a valid
> pointer.
>
> Invert the logic to fix memory leak.
>
> Signed-off-by: Jernej Skrabec
Given
>
> Signed-off-by: Jernej Skrabec
Reviewed-by: Chen-Yu Tsai
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; all endpoints in input port and adds available components to fifo.
>
> This patch doesn't do any functional change.
>
> Signed-off-by: Jernej Skrabec
Reviewed-by: Chen-Yu Tsai
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ht
to be calculated by subtracting 1 from
> +* remote output id. If this for some reason can't be done, 0
> +* is used as input port id.
> +*/
You need to call
of_node_put(port);
to drop the reference to the original port.
Otherwise,
Reviewed-by: Chen-Yu Tsai
&g
>
> Signed-off-by: Jernej Skrabec
Reviewed-by: Chen-Yu Tsai
Though I think at some point we could just have separate functions
to handle channel 0 and channel 1.
ChenYu
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On Mon, Jun 25, 2018 at 3:58 PM, Jernej Škrabec
wrote:
> Dne ponedeljek, 25. junij 2018 ob 05:51:41 CEST je Chen-Yu Tsai napisal(a):
>> On Mon, Jun 25, 2018 at 3:52 AM, Jernej Škrabec
>>
>> wrote:
>> > Dne četrtek, 21. junij 2018 ob 17:35:45 CEST je Jernej Škrabec
On Mon, Jun 25, 2018 at 3:52 AM, Jernej Škrabec
wrote:
> Dne četrtek, 21. junij 2018 ob 17:35:45 CEST je Jernej Škrabec napisal(a):
>> Dne četrtek, 21. junij 2018 ob 03:23:27 CEST je Chen-Yu Tsai napisal(a):
>> > On Thu, Jun 21, 2018 at 3:37 AM, Jernej Škrabec
>>
>>
On Thu, Jun 21, 2018 at 3:37 AM, Jernej Škrabec wrote:
> Dne sobota, 16. junij 2018 ob 07:48:38 CEST je Chen-Yu Tsai napisal(a):
>> On Sat, Jun 16, 2018 at 1:33 AM, Jernej Škrabec
> wrote:
>> > Dne petek, 15. junij 2018 ob 19:13:17 CEST je Chen-Yu Tsai napisal(a):
>&
On Sun, Jul 1, 2018 at 4:27 PM, Jernej Škrabec wrote:
> Dne četrtek, 28. junij 2018 ob 08:24:34 CEST je Chen-Yu Tsai napisal(a):
>> On Thu, Jun 28, 2018 at 12:45 PM, Jernej Škrabec
>>
>> wrote:
>> > Dne četrtek, 28. junij 2018 ob 03:51:31 CEST je Chen-Yu Tsai na
On Sun, Jul 1, 2018 at 11:13 PM, Jernej Škrabec wrote:
> Dne nedelja, 01. julij 2018 ob 15:52:55 CEST je Chen-Yu Tsai napisal(a):
>> On Sun, Jul 1, 2018 at 6:41 PM, Jernej Škrabec
> wrote:
>> > Dne četrtek, 28. junij 2018 ob 08:51:07 CEST je Chen-Yu Tsai napisal(a):
>&
On Wed, May 2, 2018 at 12:16 AM, Rob Herring wrote:
> On Mon, Apr 30, 2018 at 05:10:38PM +0530, Jagan Teki wrote:
>> Allwinner A64 has DE2 CCU which is similar to H3/H5 SoC.
>>
>> Signed-off-by: Jagan Teki
>> ---
>>
On Mon, Apr 30, 2018 at 7:40 PM, Jagan Teki wrote:
> Allwinner 64-bit SoC like H5/A64 has DesignWare HDMI so
> enable them as default.
Should we not also enable it by default for SUN8I (A83T, H3, R40?, etc.)
> Signed-off-by: Jagan Teki
>
On Mon, Apr 30, 2018 at 7:40 PM, Jagan Teki wrote:
> Allwinner 64-bit SoC like H5/A64 has DE2 CCU so enable them
> as default.
>
> Signed-off-by: Jagan Teki
> ---
> drivers/clk/sunxi-ng/Kconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
>
On Wed, May 2, 2018 at 12:17 AM, Rob Herring wrote:
> On Mon, Apr 30, 2018 at 05:10:41PM +0530, Jagan Teki wrote:
>> Allwinner A64 has DE2 pipeline similar to other Allwinner
>> SOC's like A83T, H3/H5.
>
> 'dt-bindings: ' for the subject prefix.
>
>>
>> Signed-off-by: Jagan Teki
On Sat, Jun 30, 2018 at 3:32 AM, Jernej Škrabec wrote:
> Dne četrtek, 28. junij 2018 ob 09:00:32 CEST je Chen-Yu Tsai napisal(a):
>> On Thu, Jun 28, 2018 at 12:51 PM, Jernej Škrabec
>>
>> wrote:
>> > Dne četrtek, 28. junij 2018 ob 04:19:55 CEST je Chen-Yu Tsai na
On Fri, Jan 5, 2018 at 3:28 AM, Jernej Škrabec <jernej.skra...@siol.net> wrote:
> Hi,
>
> Dne četrtek, 04. januar 2018 ob 15:45:18 CET je Chen-Yu Tsai napisal(a):
>> On Sun, Dec 31, 2017 at 5:01 AM, Jernej Skrabec <jernej.skra...@siol.net>
> wrote:
>> >
On Mon, Dec 18, 2017 at 10:57 PM, Maxime Ripard
wrote:
> The display frontend is an hardware block that can be used to implement
> some more advanced features like hardware scaling or colorspace
> conversions. It can also be used to implement the output format of
On Mon, Dec 18, 2017 at 10:57 PM, Maxime Ripard
wrote:
> Now that we have a driver, we can make use of it. This is done by
> adding a flag to our custom plane state that will trigger whether we should
> use the frontend on that particular plane or not.
>
> The
end in a given
> configuration, and will toggle the switch in that plane state so that the
> proper setup function can do their role.
>
> Reviewed-by: Neil Armstrong <narmstr...@baylibre.com>
> Signed-off-by: Maxime Ripard <maxime.rip...@free-el
On Tue, Jan 9, 2018 at 6:09 PM, Maxime Ripard
wrote:
> The display frontend is an hardware block that can be used to implement
> some more advanced features like hardware scaling or colorspace
> conversions. It can also be used to implement the output format of
ckend0 and backend1, as described in the following link:
http://elixir.free-electrons.com/linux/v4.15-rc8/source/arch/arm/boot/dts/sun6i-a31.dtsi#L1177
So with your code, both backends would end up using frontend0, and
if both display pipelines are active, one would potentially step on
the other.
On Thu, Jan 18, 2018 at 3:22 PM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> Hi,
>
> On Wed, Jan 17, 2018 at 09:43:31PM +0800, Chen-Yu Tsai wrote:
>> > if (sun4i_drv_node_is_connector(node))
>> > return 0;
>> >
>>
On Thu, Jan 11, 2018 at 3:25 AM, Jernej Skrabec wrote:
> Some SoCs, like Allwinner A83T, have to do additional cleanup when
> HDMI driver unloads. When using DW HDMI through DRM bridge API, there is
> no place to store driver's private data so it can be accessed in unbind
bf25d59cf88..900e716443b8 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_layer.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_layer.c
> @@ -201,32 +201,11 @@ struct drm_plane **sun4i_layers_init(struct drm_device
> *drm,
> struct sun4i_backend *backend = engine_to_sun4i_backe
_helper_check for now.
>
> Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Acked-by: Chen-Yu Tsai <w...@csie.org>
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On Mon, Jan 22, 2018 at 6:35 PM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> The our plane state zpos value will be set only if there's an existing
^^^ extra word
Otherwise,
Acked-by: Chen-Yu Tsai <w...@csie.org>
> state attached to the plane when cre
ne->state;
> + unsigned int priority = state->normalized_zpos;
> +
> + DRM_DEBUG_DRIVER("Setting layer %d priority to %d\n", layer,
> priority);
You might want to make the statement less ambiguous, like
"Setting layer %d's priority ..."
Otherwis
ng means it won't break if you split it out.
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..@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
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On Mon, Jan 22, 2018 at 6:35 PM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> There was a typo in the width spelling of the (unused)
> SUN4I_BACKEND_IYUVLINEWITDTH_REG macro. Fix it.
>
> Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
A
On Mon, Jan 22, 2018 at 6:35 PM, Maxime Ripard
<maxime.rip...@free-electrons.com> wrote:
> The sun4i_plane_desc structure was somehow indented to two tabulations
> instead of one as we shoud do. Fix that.
>
> Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
..@free-electrons.com>
Acked-by: Chen-Yu Tsai <w...@csie.org>
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On Fri, Feb 9, 2018 at 4:40 AM, Maxime Ripard wrote:
> On Wed, Feb 07, 2018 at 01:49:59PM +0100, Giulio Benetti wrote:
>> Hi,
>>
>> Il 07/02/2018 11:39, Maxime Ripard ha scritto:
>> > On Wed, Jan 24, 2018 at 08:37:28PM +0100, Giulio Benetti wrote:
>> > Also, how was
Hi,
On Wed, Feb 21, 2018 at 5:20 PM, Maxime Ripard
wrote:
> From: Maxime Ripard
>
> The LHR050H41 panel is the panel shipped with the BananaPi M2-Magic. Add a
> driver for it.
So I distinctly remember questioning the vendor name the
On Mon, Feb 26, 2018 at 5:38 PM, Maxime Ripard
wrote:
> Hi,
>
> On Sat, Feb 24, 2018 at 10:45:31PM +0100, Jernej Skrabec wrote:
>> Some NM PLLs doesn't work well when their output clock rate is set below
>> certain rate.
>>
>> Add support for that constrain.
>
> In such
mically checked and assigned, we
> can remove the static definition.
>
> Signed-off-by: Maxime Ripard <maxime.rip...@bootlin.com>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
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On Thu, Feb 22, 2018 at 10:34 PM, Maxime Ripard
<maxime.rip...@bootlin.com> wrote:
> On Thu, Feb 22, 2018 at 10:17:38PM +0800, Chen-Yu Tsai wrote:
>> On Sat, Feb 17, 2018 at 1:39 AM, Maxime Ripard
>> <maxime.rip...@bootlin.com> wrote:
>> > Our backend supports
g zpos
> starting with the pipe 0. When and if we encounter our alpha plane, we put
> it and all the other subsequent planes in the second pipe.
>
> Signed-off-by: Maxime Ripard <maxime.rip...@bootlin.com>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
_
Signed-off-by: Maxime Ripard <maxime.rip...@bootlin.com>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
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On Sat, Feb 17, 2018 at 1:39 AM, Maxime Ripard
<maxime.rip...@bootlin.com> wrote:
> Our backend supports a per-plane alpha property. Support it through our new
> helper.
>
> Signed-off-by: Maxime Ripard <maxime.rip...@bootlin.com>
Reviewed-by: Chen-Yu Tsai <w...@cs
On Fri, Dec 22, 2017 at 8:22 PM, Icenowy Zheng wrote:
> Allwinner A64's DE2 needs to claim a section of SRAM (SRAM C) to work.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng
> ---
> drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 32
On Fri, Dec 22, 2017 at 8:22 PM, Icenowy Zheng wrote:
> The H3/H5 SoCs have a HDMI output and a TV Composite output.
>
> Add simplefb nodes for these outputs.
>
> Signed-off-by: Icenowy Zheng
> ---
> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 29
On Fri, Dec 22, 2017 at 8:22 PM, Icenowy Zheng wrote:
> This patchset adds support for the SimpleFB on Allwinner SoCs with
> "Display Engine 2.0".
>
> PATCH 1 to PATCH 3 are DE2 CCU fixes for H3/H5 SoCs.
>
> PATCH 4 adds the pipeline strings for DE2 SimpleFB.
>
> PATCH 5 to 7
On Sun, Dec 31, 2017 at 5:01 AM, Jernej Skrabec wrote:
> TCON1 also has M divider, contrary to TCON0.
>
> Fixes: 05359be1176b ("clk: sunxi-ng: Add driver for A83T CCU")
>
> Signed-off-by: Jernej Skrabec
Added "And the mux is only 2 bits wide,
On Wed, Dec 27, 2017 at 12:10 PM, Icenowy Zheng <icen...@aosc.io> wrote:
> 在 2017年12月27日星期三 CST 下午12:09:41,Chen-Yu Tsai 写道:
>> On Fri, Dec 22, 2017 at 8:22 PM, Icenowy Zheng <icen...@aosc.io> wrote:
>> > This patchset adds support for the SimpleFB on Allwinner SoCs
On Fri, Dec 22, 2017 at 8:22 PM, Icenowy Zheng wrote:
> This patchset adds support for the SimpleFB on Allwinner SoCs with
> "Display Engine 2.0".
>
> PATCH 1 to PATCH 3 are DE2 CCU fixes for H3/H5 SoCs.
>
> PATCH 4 adds the pipeline strings for DE2 SimpleFB.
>
> PATCH 5 to 7
On Sun, Dec 31, 2017 at 5:01 AM, Jernej Skrabec wrote:
> For example, A83T have nmp plls which are modelled as nkmp plls. Since k
> is not specified, it has offset 0, shift 0 and lowest value 1. This
> means that LSB bit is always set to 1, which may change clock rate.
>
er.
>
> Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
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CRTC, our TCON, is enabled
> when we perform an atomic_commit.
>
> Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <w...@csie.org>
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h
for it in the DRM driver, let's
> enable its DT node.
>
> Signed-off-by: Maxime Ripard <maxime.rip...@free-electrons.com>
Acked-by: Chen-Yu Tsai <w...@csie.org>
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On Tue, Aug 14, 2018 at 1:43 PM, Icenowy Zheng wrote:
> 在 2018-07-24二的 14:37 +0200,Maxime Ripard写道:
>> On Sun, Jul 22, 2018 at 04:43:56PM +0200, Jernej Škrabec wrote:
>> > Hi Maxime,
>> >
>> > Dne sreda, 11. julij 2018 ob 10:30:36 CEST je Maxime Ripard
>> > napisal(a):
>> > > On Tue, Jul 10, 2018
crashing upon probing.
The compatibles should be reinstated for the next release.
Signed-off-by: Chen-Yu Tsai
---
This is for 4.19-rc to fix the boot crash seen on the R40.
This should go in drm-misc-fixes and into Linus' tree ASAP.
Once merged, the branch should also be merged into drm-misc
On Wed, Jul 18, 2018 at 6:54 PM, Jagan Teki wrote:
> Allwinner A64 has display engine pipeline like other Allwinner SOC's
> A83T/H3/H5.
>
> A64 behaviour similar to Allwinner A83T where
> Mixer0 => TCON0 => LVDS/RGB/MIPI-DSI
> Mixer1 => TCON1 => HDMI
> as per Display System Block Diagram from
On Sun, Sep 2, 2018 at 3:27 PM Jernej Skrabec wrote:
>
> This series adds support for Display Engine 3.0 and HDMI 2.0a, which
> can be found on H6 SoC.
>
> Display Engine 3.0 in comparison to 2.0 mostly adds features needed for
> displaying and processing 10-bit and AFBC formats, which are not
be dithering support that will be added in a
later patch, which looks at properties tied to the connector to
determine whether dithering should be enabled or not.
Signed-off-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions
-by: Chen-Yu Tsai
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 61 ++
1 file changed, 61 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index d6f9d5f3b15b..4834c90b4912 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b
Dithering is only supported for TCON channel 0. Throughout the datasheet
all the names associated with these register are prefixed "TCON0",
instead of "TCON". The only exception is the control register
"TCON_FRM_CTL_REG".
Rename the macros to reflect this
thing, but it is nevertheless included for completeness. There
is also a FT5306 capacitive touchscreen controller.
This should not be confused with the other 7" LCD that is LVDS based
and has a resolution of 1024x600.
This patch enables all of the above for the BPI-M1+.
Signed-off-by: Ch
On the A20, as well as many other Allwinner SoCs, the PD pingroup has
the LCD0 RGB output functions.
Add a pinmux setting for RGB888 output from LCD0, so boards and tablets
with parallel RGB LCD panels may reference it.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun7i-a20.dtsi | 11
ule either
supports DSI, or DSI + 24-bit RGB. DSI is converted to 24-bit RGB via
an onboard ICN6211 MIPI DSI - RGB bridge chip, then fed to the panel
itself.
Signed-off-by: Chen-Yu Tsai
---
.../display/panel/bananapi,s070wv20-ct16.txt | 12 +
drivers/gpu/drm/panel/panel-simple.c
ters so the LCD backlight wouldn't be
completely black.
Regards
ChenYu
Chen-Yu Tsai (5):
drm/sun4i: tcon: Pass drm_encoder * into sun4i_tcon0_mode_set_cpu
drm/sun4i: tcon: Rename Dithering related register macros
drm/panel: simple: Add support for Banana Pi 7" S070WV20-CT16 panel
ARM: dt
On Fri, Sep 7, 2018 at 3:22 PM Icenowy Zheng wrote:
>
> When adding support for A64 HDMI PHY in 4.19, we assumed that the two
> PLL-VIDEOs can both feed the HDMI PHY clock. However experiments show
> that the mux bit discovered in R40 blob is not applicable on A64. This
> is not discovered, as
iggest number of possible outputs from all Allwinner SoC.
> Because of that, add new compatible for it.
>
> Signed-off-by: Jernej Skrabec
Reviewed-by: Chen-Yu Tsai
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On Sat, Jul 7, 2018 at 1:50 AM, Jernej Skrabec wrote:
> R40 has versatile display pipeline. It supports two simultanious outputs
> on various outputs (TVE, VGA, HDMI, MIPI DSI, LCD).
>
> Signed-off-by: Jernej Skrabec
Reviewed-by: Chen-Yu Tsai
___
On Sat, Jul 7, 2018 at 1:50 AM, Jernej Skrabec wrote:
> R40 has pretty unique display pipeline. Because of that, H3 display
> engine compatible fallback should be removed.
>
> Fixes: 05a43a262d03 ("ARM: dts: sun8i: r40: Add HDMI pipeline")
>
> Signed-off-by: Jernej Sk
On Sat, Jul 7, 2018 at 1:51 AM, Jernej Skrabec wrote:
> There is no need to acquire reference to clock just to get its name.
>
> This commit just cleans up the code. There is no functional change.
>
> Signed-off-by: Jernej Skrabec
Reviewed-b
engine search algorithm")
>
> Signed-off-by: Jernej Skrabec
Reviewed-by: Chen-Yu Tsai
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On Sat, Jul 7, 2018 at 1:51 AM, Jernej Skrabec wrote:
> TCON description is expanded with R40 TV TCON compatible. It is a bit
> special, because it is connected to TCON TOP instead directly to mixer
> and it needs special handling.
>
> Signed-off-by: Jernej Skrabec
Reviewed-b
get_remote_node() which also lowers number of
> cases where error handling has to be performed.
Good job!
> Fixes: 57e23de02f48 ("drm/sun4i: DW HDMI: Expand algorithm for possible
> crtcs")
>
> Signed-off-by: Jernej Skrabec
Reviewed-by: Chen-Yu Tsai
_
On Sat, Jul 7, 2018 at 1:51 AM, Jernej Skrabec wrote:
> Currently, TCON supports 2 ways to match TCON with engine (mixer in this
> case). Old way is to just traverse of graph backwards and compare node
> pointer. New way is to match TCON and engine by their respective ids.
> All SoCs with DE2
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