Hi Nirmoy,
On Fri, May 17, 2024 at 04:00:02PM +0200, Nirmoy Das wrote:
> On 5/17/2024 1:25 PM, Andi Shyti wrote:
> > If we timeout while waiting for an FLR reset, there is nothing we
> > can do and i915 doesn't have any control on it. In any case the
> > system is s
of an error.
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10955
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/intel_uncore.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index
Following the guidelines it takes 3 seconds to perform an FLR
reset. Let's give it a bit more slack because this time can
change depending on the platform and on the firmware
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10955
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915
fucntions without any effect.
While at it, increase the timeout.
Thanks,
Andi
Andi Shyti (2):
drm/i915: Increase FLR timeout from 3s to 9s
drm/i915: Don't treat FLR resets as errors
drivers/gpu/drm/i915/intel_uncore.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions
n't have the latest
> changes made by GPU.
>
> Cc: Andi Shyti
> Cc: Janusz Krzysztofik
> Cc: Jonathan Cavitt
> Signed-off-by: Nirmoy Das
you can add:
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Janusz,
On Tue, Apr 23, 2024 at 06:23:10PM +0200, Janusz Krzysztofik wrote:
> From: Chris Wilson
>
> The breadcrumbs use a GT wakeref for guarding the interrupt, but are
> disarmed during release of the engine wakeref. This leaves a hole where
> we may attach a breadcrumb just as the engine
Hi,
On Fri, May 03, 2024 at 03:34:12PM -0400, Rodrigo Vivi wrote:
> On Fri, May 03, 2024 at 06:13:24PM +, Easwar Hariharan wrote:
> > I2C v7, SMBus 3.2, and I3C 1.1.1 specifications have replaced "master/slave"
> > with more appropriate terms. Inspired by and following on to Wolfram's
> >
Hi,
On Fri, Apr 26, 2024 at 02:07:23AM +0200, Andi Shyti wrote:
> We missed setting the CCS mode during resume and engine resets.
> Create a workaround to be added in the engine's workaround list.
> This workaround sets the XEHP_CCS_MODE value at every reset.
>
> The issue ca
encounter a fence timeout:
Fence expiration time out i915-:03:00.0:clpeak[2387]:2!
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10895
Fixes: 6db31251bb26 ("drm/i915/gt: Enable only one CCS for compute workload")
Reported-by: Gnattu OC
Signed-off-by: Andi Shyti
Hi Nirmoy,
> > > Currently intel_gt_reset() kills the GuC and then resets requested
> > > engines. This is problematic because there is a dedicated CSB FIFO
> > > which only GuC can access and if that FIFO fills up, the hardware
> > > will block on the next context switch until there is space
Hi Nirmoy,
On Tue, Apr 23, 2024 at 11:02:06AM +0200, Nirmoy Das wrote:
> On 4/17/2024 12:49 AM, Andi Shyti wrote:
...
> void intel_engines_driver_register(struct drm_i915_private *i915)
> {
> - u16 name_instance, other_instance = 0;
> + u16
t(struct intel_gt *gt,
>
> intel_overlay_reset(gt->i915);
>
> + /* sanitize uC after engine reset */
> + if (!intel_uc_uses_guc_submission(>uc))
> + intel_uc_reset_prepare(>uc);
Reviewed-by: Andi Shyti
Thanks,
Andi
_engines() next to
> intel_gt_reset_engine() to make diff simple(John)
>
> Cc: John Harrison
> Signed-off-by: Nirmoy Das
Reviewed-by: Andi Shyti
Thanks,
Andi
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
b/drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c
index 044219c5960a..d0f181a8e73e 100644
This reverts commit ea315f98e5d6d3191b74beb0c3e5fc16081d517c.
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 17 -
1 file changed, 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 8c44af1c3451..476651bd0a21
/-/issues/10895
Andi Shyti (2):
Revert "drm/i915/gt: Do not generate the command streamer for all the
CCS"
drm/i915/gt: Force ccs_mode 4
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 17 -
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 12
2 files
itly during device unbind.
>
> v2: Change commit message and other minor code changes
> v3: Cleanup from i915_hwmon_register on error (Armin Wolf)
> v4: Eliminate potential static analyzer warning (Rodrigo)
> Eliminate fetch_and_zero (Jani)
> v5: Restore previous logic for ddat_gt->hwmon_dev error return (Andi)
Thanks!
Reviewed-by: Andi Shyti
Andi
Hi Ashutosh,
> @@ -839,16 +837,38 @@ void i915_hwmon_register(struct drm_i915_private *i915)
> if (!hwm_gt_is_visible(ddat_gt, hwmon_energy,
> hwmon_energy_input, 0))
> continue;
>
> - hwmon_dev = devm_hwmon_device_register_with_info(dev,
>
For the upcoming changes we need a cleaner way to build the list
of uabi engines.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Andi Shyti
---
Hi,
just sending this patch to unburden the coming series from this
single patch inherited from a previously sent series.
Andi
drivers/gpu/drm/i915/gt
> removed.
>
> Cleans up clang scan build warning:
> drivers/gpu/drm/i915/gem/selftests/i915_gem_mman.c:1075:5: warning: Value
> stored to 'err' is never read [deadcode.DeadStores]
>
> Signed-off-by: Colin Ian King
Reviewed-by: Andi Shyti
Thanks,
Andi
> entries.
>
> Cc: Joonas Lahtinen
> Cc: Lucas De Marchi
> Cc: Oded Gabbay
> Cc: Rodrigo Vivi
> Cc: Thomas Hellström
> Cc: Tvrtko Ursulin
> Signed-off-by: Jani Nikula
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Jani,
On Wed, Apr 10, 2024 at 01:26:15PM +0300, Jani Nikula wrote:
> Clean up the top level include/drm directory by grouping all the Intel
> specific files under a common subdirectory.
>
> v2: Also fix comment in intel_pci_config.h (Ilpo)
>
> Cc: Daniel Vetter
> Cc: Dave Airlie
> Cc:
nt
intel_lpe_audio.h. Can't they be merged?
And, perhaps, we could also think of dropping the intel_ prefix
for the files inside drm/intel/.
In any case,
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Jani,
On Wed, Apr 10, 2024 at 01:05:11PM +0300, Jani Nikula wrote:
> Clean up the top level include/drm directory by grouping all the Intel
> specific files under a common subdirectory.
>
> Cc: Daniel Vetter
> Cc: Dave Airlie
> Cc: Lucas De Marchi
> Cc: Tomas Winkler
> Cc: Jaroslav Kysela
> Signed-off-by: Jani Nikula
Reviewed-by: Andi Shyti
Thanks,
Andi
On Wed, Apr 10, 2024 at 01:05:09PM +0300, Jani Nikula wrote:
> Clean up the top level include/drm directory by grouping all the Intel
> specific files under a common subdirectory.
>
> Cc: Daniel Vetter
> Cc: Dave Airlie
> Cc: Lucas De Marchi
> Signed-off-by: Jani Nikul
Hi Jani,
On Wed, Apr 10, 2024 at 01:05:08PM +0300, Jani Nikula wrote:
> Use <> instead of "" for including headers from include/, even if the
> file is in the same directory.
>
> Signed-off-by: Jani Nikula
Reviewed-by: Andi Shyti
Thanks,
Andi
ncel is safe (from a lockdep perspective) or not.
> Instead, use the actual reset mutex state (both the genuine one and
> the custom rolled BACKOFF one).
>
> Fixes: 0e00a8814eec ("drm/i915/guc: Avoid circular locking issue on busyness
> flush")
> Signed-off-by: John Harr
Hi,
On Fri, Mar 29, 2024 at 10:28:14AM -0700, Easwar Hariharan wrote:
> On 3/29/2024 10:16 AM, Andi Shyti wrote:
> > Hi Easwar,
> >
> > On Fri, Mar 29, 2024 at 05:00:26PM +, Easwar Hariharan wrote:
> >> I2C v7, SMBus 3.2, and I3C specifications have replaced &
Hi Easwar,
On Fri, Mar 29, 2024 at 05:00:26PM +, Easwar Hariharan wrote:
> I2C v7, SMBus 3.2, and I3C specifications have replaced "master/slave"
I don't understand why we forget that i3c is 1.1.1 :-)
> with more appropriate terms. Inspired by and following on to Wolfram's
> series to fix
Hi Nirmoy,
On Tue, Mar 26, 2024 at 01:05:37PM +0100, Nirmoy Das wrote:
> On 3/26/2024 12:12 PM, Andi Shyti wrote:
> > > > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > > b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > > >
Hi Nirmoy,
On Thu, Mar 28, 2024 at 09:54:12AM +0100, Nirmoy Das wrote:
> On 3/27/2024 9:05 PM, Andi Shyti wrote:
> > Commit 9bb66c179f50 ("drm/i915: Reserve some kernel space per
> > vm") reduces the available VM space of one page in order to apply
> > Wa
Hi,
On Thu, Mar 28, 2024 at 08:18:33AM +0100, Andi Shyti wrote:
> Anyone using 'dev_priv' instead of 'i915' in a cleaned-up area
> should be fined and required to do community service for a few
> days.
Not to scare people off, I would add another sentence in between:
"Using
5/dg2: Drop force_probe requirement")
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matt Roper
Cc: # v6.2+
Reviewed-by: Matt Roper
Acked-by: Michal Mrozek
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_ccs_m
t;)
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matt Roper
Cc: # v6.2+
Acked-by: Michal Mrozek
Reviewed-by: Matt Roper
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engi
The hardware should not dynamically balance the load between CCS
engines. Wa_14019159160 recommends disabling it across all
platforms.
Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matt Roper
C
-> v2
- In Patch 1 use the correct workaround number (thanks Matt).
- In Patch 2 do not add the extra CCS engines to the exposed
UABI engine list and adapt the engine counting accordingly
(thanks Tvrtko).
- Reword the commit of Patch 2 (thanks John).
Andi Shyti (3):
drm/i915/gt: Disabl
Hi Matt,
> > + /*
> > +* Do not create the command streamer for CCS slices beyond the first.
> > +* All the workload submitted to the first engine will be shared among
> > +* all the slices.
> > +*
> > +* Once the user will be allowed to customize the CCS mode, then this
> >
Anyone using 'dev_priv' instead of 'i915' in a cleaned-up area
should be fined and required to do community service for a few
days.
I thought I had cleaned up the 'gem/' directory in the past, but
still, old aficionados of the 'dev_priv' name keep sneaking it
in.
Signed-off-by: Andi Shyti
Cc
Hi,
On Wed, Mar 27, 2024 at 09:05:46PM +0100, Andi Shyti wrote:
> Commit 9bb66c179f50 ("drm/i915: Reserve some kernel space per
> vm") reduces the available VM space of one page in order to apply
> Wa_16018031267 and Wa_16018063123.
>
> This page was reserved indiscrimit
("drm/i915: Reserve some kernel space per vm")
Signed-off-by: Andi Shyti
Cc: Andrzej Hajda
Cc: Chris Wilson
Cc: Jonathan Cavitt
Cc: Nirmoy Das
---
drivers/gpu/drm/i915/gt/gen8_ppgtt.c | 3 +++
drivers/gpu/drm/i915/gt/intel_gt.c | 6 ++
drivers/gpu/drm/i915/gt/intel_gt.h |
5/dg2: Drop force_probe requirement")
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matt Roper
Cc: # v6.2+
Reviewed-by: Matt Roper
Acked-by: Michal Mrozek
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_ccs_m
t;)
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matt Roper
Cc: # v6.2+
Acked-by: Michal Mrozek
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/d
The hardware should not dynamically balance the load between CCS
engines. Wa_14019159160 recommends disabling it across all
platforms.
Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matt Roper
C
ch 1, in a cleaner
outcome.
v1 -> v2
- In Patch 1 use the correct workaround number (thanks Matt).
- In Patch 2 do not add the extra CCS engines to the exposed
UABI engine list and adapt the engine counting accordingly
(thanks Tvrtko).
- Reword the commit of Patch 2 (thanks John).
Andi Shy
Hi Matt,
On Tue, Mar 26, 2024 at 02:30:33PM -0700, Matt Roper wrote:
> On Tue, Mar 26, 2024 at 07:42:34PM +0100, Andi Shyti wrote:
> > On Tue, Mar 26, 2024 at 09:03:10AM -0700, Matt Roper wrote:
> > > On Wed, Mar 13, 2024 at 09:19:50PM +0100
Hi Matt,
On Tue, Mar 26, 2024 at 09:03:10AM -0700, Matt Roper wrote:
> On Wed, Mar 13, 2024 at 09:19:50PM +0100, Andi Shyti wrote:
> > + /*
> > +* Do not create the command streamer for CCS slices
> > +* beyond the fi
Hi Michal, Mark,
can you please ack from your side this first batch of changes?
Thanks,
Andi
On Wed, Mar 13, 2024 at 09:19:48PM +0100, Andi Shyti wrote:
> Hi,
>
> this series does basically two things:
>
> 1. Disables automatic load balancing as adviced by the hardware
>
Joonas,
> 1. Disables automatic load balancing as adviced by the hardware
>workaround.
do we need a documentation update here?
Andi
Hi Janusz,
On Tue, Mar 05, 2024 at 03:35:05PM +0100, Janusz Krzysztofik wrote:
> Object debugging tools were sporadically reporting illegal attempts to
> free a still active i915 VMA object when parking a GT believed to be idle.
>
> [161.359441] ODEBUG: free active (active state 0) object:
Hi Janusz and Chris,
> Fixes: 22b7a426bbe1 ("drm/i915/execlists: Preempt-to-busy")
> Closes: https://gitlab.freedesktop.org/drm/intel/issues/10154
> Signed-off-by: Chris Wilson
> Cc: Mika Kuoppala
> Signed-off-by: Janusz Krzysztofik
> Cc: Chris Wilson
> Cc: # v5.4+
with the tags rearranged
Hi Nirmoy,
...
> > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > index a2195e28b625..57a2dda2c3cc 100644
> > --- a/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > +++ b/drivers/gpu/drm/i915/gem/i915_gem_mman.c
> > @@ -276,7 +276,7 @@
son
.
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Lionel Landwerlin
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 8 +---
drivers/gpu/drm/i915/i915_mm.c | 12 +++-
drivers/gpu/drm/i915/i915_mm.h | 3 ++-
3 files changed, 18 insertions(+), 5 deletions(-)
diff --
n the user requests
the GTT size through ioctl (I915_CONTEXT_PARAM_GTT_SIZE).
Fixes: 9bb66c179f50 ("drm/i915: Reserve some kernel space per vm")
Signed-off-by: Andi Shyti
Cc: Andrzej Hajda
Cc: Chris Wilson
Cc: Lionel Landwerlin
Cc: Michal Mrozek
Cc: Nirmoy Das
Cc: # v6.2+
Acked-by:
Hi Michal,
On Mon, Mar 18, 2024 at 05:21:54AM +, Mrozek, Michal wrote:
> > > Lionel, Michal, thoughts?
> Compute UMD needs to know exact GTT total size.
the problem is that we cannot apply the workaround without
reserving one page from the GTT total size and we need to apply
the workaround.
Hi Tvrtko,
On Wed, Mar 20, 2024 at 03:40:18PM +, Tvrtko Ursulin wrote:
> On 20/03/2024 15:06, Andi Shyti wrote:
> > Ping! Any thoughts here?
>
> I only casually observed the discussion after I saw Matt suggested further
> simplifications. As I understood it, you will b
Ping! Any thoughts here?
Andi
On Wed, Mar 13, 2024 at 09:19:48PM +0100, Andi Shyti wrote:
> Hi,
>
> this series does basically two things:
>
> 1. Disables automatic load balancing as adviced by the hardware
>workaround.
>
> 2. Assigns all the CCS slices to one sing
# v5.4+
this tag list is a bit confusing. Let's keep all Cc's together
and, besides, Cc'eing the author looks a bit redundant.
No need to resend also because I retriggered another round of
test.
Reviewed-by: Andi Shyti
Thanks,
Andi
Hi Nirmoy,
> > In Mesa we've been relying on I915_CONTEXT_PARAM_GTT_SIZE so as long as
> > that is adjusted by the kernel
>
> What do you mean by adjusted by, should it be a aligned size?
>
> I915_CONTEXT_PARAM_GTT_SIZE ioctl is returning vm->total which is
> adjusted(reduced by a page).
>
>
5/dg2: Drop force_probe requirement")
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matt Roper
Cc: # v6.2+
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.c | 39 +
drivers/gpu/drm/i915/gt/intel_gt_
t;)
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matt Roper
Cc: # v6.2+
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 20
1 file changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
b/drivers/gpu/d
The hardware should not dynamically balance the load between CCS
engines. Wa_14019159160 recommends disabling it across all
platforms.
Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matt Roper
C
unting accordingly
(thanks Tvrtko).
- Reword the commit of Patch 2 (thanks John).
Andi Shyti (3):
drm/i915/gt: Disable HW load balancing for CCS
drm/i915/gt: Do not generate the command streamer for all the CCS
drm/i915/gt: Enable only one CCS for compute workload
drivers/gpu
Commit 9bb66c179f50 ("drm/i915: Reserve some kernel space per
vm") has reserved an object for kernel space usage.
Userspace, though, needs to know the full address range.
Fixes: 9bb66c179f50 ("drm/i915: Reserve some kernel space per vm")
Signed-off-by: Andi Shyti
Cc: Andr
Hi Janusz,
On Mon, Mar 11, 2024 at 09:34:58PM +0100, Janusz Krzysztofik wrote:
> In i915 hwmon sysfs getter path we now take a hwmon_lock, then acquire an
> rpm wakeref. That results in lock inversion:
>
> <4> [197.079335] ==
> <4>
Hi Nirmoy,
On Tue, Mar 12, 2024 at 12:18:15PM +0100, Nirmoy Das wrote:
> Caching mode is HW dependent so pick a correct one using
> intel_gt_coherent_map_type().
>
> Cc: Andi Shyti
> Cc: Janusz Krzysztofik
> Cc: Jonathan Cavitt
> Closes: https://gitlab.freedesktop.org/drm
On Tue, Mar 12, 2024 at 10:08:33AM -0700, Matt Roper wrote:
> On Fri, Mar 08, 2024 at 09:22:17PM +0100, Andi Shyti wrote:
> > For the upcoming changes we need a cleaner way to build the list
> > of uabi engines.
> >
> > Suggested-by: Tvrtko Ursulin
> > Signed-of
Hi Matt,
...
> > #define GEN12_RCU_MODE _MMIO(0x14800)
> > #define GEN12_RCU_MODE_CCS_ENABLEREG_BIT(0)
> > +#define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1)
>
> Nitpick: we usually order register bits in descending order. Aside from
+0xb5/0x100
>
> Acquire the wakeref before the lock and hold it as long as the lock is
> also held. Follow that pattern across the whole source file where similar
> lock inversion can happen.
>
> v2: Keep hardware read under the lock so the whole operation of updating
> energy from ha
Hi Nirmoy,
On Tue, Mar 12, 2024 at 12:18:15PM +0100, Nirmoy Das wrote:
> Caching mode is HW dependent so pick a correct one using
> intel_gt_coherent_map_type().
>
> Cc: Andi Shyti
> Cc: Janusz Krzysztofik
> Cc: Jonathan Cavitt
> Closes: https://gitlab.freedesktop.org/drm
5/dg2: Drop force_probe requirement")
Requires: 075e003a9e22 ("drm/i915/gt: Refactor uabi engine class/instance list
creation")
Requires: 58b935268238 ("drm/i915/gt: Disable tests for CCS engines beyond the
first")
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joona
In anticipation of the upcoming commit that will operate with
only one CCS stream, when more than one CCS slice is present,
create a new for_each_available_engine() that excludes CCS
engines beyond the forst. Begin using it in the hangcheck
selftest.
Signed-off-by: Andi Shyti
---
drivers/gpu
For the upcoming changes we need a cleaner way to build the list
of uabi engines.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Andi Shyti
Cc: # v6.2+
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 29 -
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git
The hardware should not dynamically balance the load between CCS
engines. Wa_14019159160 recommends disabling it across all
platforms.
Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matt Roper
C
f Patch 2 (thanks John).
Andi Shyti (4):
drm/i915/gt: Disable HW load balancing for CCS
drm/i915/gt: Refactor uabi engine class/instance list creation
drm/i915/gt: Disable tests for CCS engines beyond the first
drm/i915/gt: Enable only one CCS for compute workload
drivers
Hi John,
...
> > > > +
> > > > + /*
> > > > +* Wa_14019159160: disable the automatic CCS load
> > > > balancing
> > > I'm still a bit concerned that this doesn't really match what this
> > > specific workaround is asking us to do. There seems to be an agreement
>
Hi Matt,
> > +static void intel_gt_apply_ccs_mode(struct intel_gt *gt)
> > +{
> > + u32 mode;
> > + int cslice;
> > +
> > + if (!IS_DG2(gt->i915))
> > + return;
> > +
> > + /* Set '0' as a default CCS id to all the cslices */
> > + mode = 0;
> > +
> > + for (cslice = 0;
Hi Matt,
On Wed, Mar 06, 2024 at 03:46:09PM -0800, Matt Roper wrote:
> On Wed, Mar 06, 2024 at 02:22:45AM +0100, Andi Shyti wrote:
> > The hardware should not dynamically balance the load between CCS
> > engines. Wa_14019159160 recommends disabling it across all
> > plat
5/dg2: Drop force_probe requirement")
Requires: 97aba5e46038 ("drm/i915/gt: Refactor uabi engine class/instance list
creation")
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matt Roper
Cc: # v6.2+
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 11 +++
For the upcoming changes we need a cleaner way to build the list
of uabi engines.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Andi Shyti
Cc: # v6.2+
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 29 -
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git
The hardware should not dynamically balance the load between CCS
engines. Wa_14019159160 recommends disabling it across all
platforms.
Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matt Roper
C
accordingly (thanks
Tvrtko).
- Reword the commit of Patch 2 (thanks John).
Andi Shyti (3):
drm/i915/gt: Disable HW load balancing for CCS
drm/i915/gt: Refactor uabi engine class/instance list creation
drm/i915/gt: Enable only one CCS for compute workload
drivers/gpu/drm/i915/gt/intel
Hi Janusz,
On Thu, Feb 22, 2024 at 12:32:40PM +0100, Janusz Krzysztofik wrote:
> Third argument of i915_request_wait() accepts a timeout value in jiffies.
> Most users pass either a simple HZ based expression, or a result of
> msecs_to_jiffies(), or MAX_SCHEDULE_TIMEOUT, or a very small number
Hi Janusz,
On Wed, Feb 28, 2024 at 04:24:41PM +0100, Janusz Krzysztofik wrote:
> While trying to reproduce some other issues reported by CI for i915
> hangcheck live selftest, I found them hidden behind timeout failures
> reported by igt_hang_sanitycheck -- the very first hangcheck test case
>
Hi Joonas,
...
> > void intel_engines_driver_register(struct drm_i915_private *i915)
> > {
> > - u16 name_instance, other_instance = 0;
> > + u16 class_instance[I915_LAST_UABI_ENGINE_CLASS + 1] = { };
>
> Do you mean this to be size I915_LAST_UABI_ENGINE_CLASS + 2? Because ...
by new auxiliary drivers that didn't exist before and now are
> loaded in parallel with the i915 module also when loaded in selftest mode,
> relax our expectations on time consumed by the sanity check request before
> it completes.
>
> Signed-off-by: Janusz Krzysztofik
I'm OK with it...
Reviewed-by: Andi Shyti
Thanks,
Andi
i915/selftest: Fix workarounds selftest for GuC
> submission")
> Signed-off-by: Janusz Krzysztofik
> Cc: Rahul Kumar Singh
> Cc: John Harrison
> Cc: Matthew Brost
Reviewed-by: Andi Shyti
Thanks,
Andi
5/dg2: Drop force_probe requirement")
Requires: 4e4f77d74878 ("drm/i915/gt: Refactor uabi engine class/instance list
creation")
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matt Roper
Cc: # v6.2+
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 11
The hardware should not dynamically balance the load between CCS
engines. Wa_14019159160 recommends disabling it across all
platforms.
Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matt Roper
C
list
creation")
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c
b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index cf8f24ad88f6..ec5bcd1c1ec4 100644
--- a/
For the upcoming changes we need a cleaner way to build the list
of uabi engines.
Suggested-by: Tvrtko Ursulin
Signed-off-by: Andi Shyti
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 29 -
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm
BI
engine list and adapt the engine counting accordingly (thanks
Tvrtko).
- Reword the commit of Patch 2 (thanks John).
Andi Shyti (4):
drm/i915/gt: Refactor uabi engine class/instance list creation
drm/i915/gt: Do not exposed fused off engines.
drm/i915/gt: Disable HW load balancing for C
Hi Jani,
thanks, there has been a v2 after this and your comments have
been addressed somehow.
There will be a v3, as well.
Thanks,
Andi
On Tue, Feb 27, 2024 at 02:18:01PM +0200, Jani Nikula wrote:
> On Tue, 20 Feb 2024, Andi Shyti wrote:
> > Since CCS automatic load balancing is dis
Hi Matt,
first of all thanks a lot for the observations you are raising.
On Wed, Feb 21, 2024 at 12:51:04PM -0800, Matt Roper wrote:
> On Wed, Feb 21, 2024 at 01:12:18AM +0100, Andi Shyti wrote:
> > On Tue, Feb 20, 2024 at 03:39:18PM -0800, Matt Roper wrote:
> > > On Tue, Feb
Hi Tvrtko,
On Wed, Feb 21, 2024 at 08:19:34AM +, Tvrtko Ursulin wrote:
> On 21/02/2024 00:14, Andi Shyti wrote:
> > On Tue, Feb 20, 2024 at 02:48:31PM +, Tvrtko Ursulin wrote:
> > > On 20/02/2024 14:35, Andi Shyti wrote:
> > > > Enable only one CCS engine b
Hi Tvrtko,
On Tue, Feb 20, 2024 at 02:48:31PM +, Tvrtko Ursulin wrote:
> On 20/02/2024 14:35, Andi Shyti wrote:
> > Enable only one CCS engine by default with all the compute sices
>
> slices
Thanks!
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c
>
Hi Matt,
thanks a lot for looking into this.
On Tue, Feb 20, 2024 at 03:39:18PM -0800, Matt Roper wrote:
> On Tue, Feb 20, 2024 at 03:35:26PM +0100, Andi Shyti wrote:
[...]
> > diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c
> > b/drivers/gpu/drm/i915/gt/intel_engine_u
Hi,
[...]
> diff --git a/drivers/gpu/drm/i915/i915_query.c
> b/drivers/gpu/drm/i915/i915_query.c
> index 3baa2f54a86e..d5a5143971f5 100644
> --- a/drivers/gpu/drm/i915/i915_query.c
> +++ b/drivers/gpu/drm/i915/i915_query.c
> @@ -124,6 +124,7 @@ static int query_geometry_subslices(struct
>
5/dg2: Drop force_probe requirement")
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matt Roper
Cc: # v6.2+
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 9 +
drivers/gpu/drm/i915/gt/intel_gt.c | 11 +++
drivers/gpu/drm/i915/gt/intel
The hardware should not dynamically balance the load between CCS
engines. Wa_14019159160 recommends disabling it across all
platforms.
Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement")
Signed-off-by: Andi Shyti
Cc: Chris Wilson
Cc: Joonas Lahtinen
Cc: Matt Roper
C
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