I just wanted to contribute the following piece of information that might
help with R300 lockups. I do not know whether it applies or not in this
case, but just something to be aware about.
Radeon has a memory controller which translates internal address space of
the chip into accesses of
On Saturday 04 June 2005 15:01, Vladimir Dergachev wrote:
I just wanted to contribute the following piece of information that
might
help with R300 lockups. I do not know whether it applies or not in this
case, but just something to be aware about.
Radeon has a memory controller which
Are you sure it uses PCI? I'm assuming that the destination address for
scratch writeback is controlled by the RADEON_SCRATCH_ADDR register. This
register is programmed to a value that falls within the AGP area (as
defined by RADEON_MC_AGP_LOCATION) if I understand the code correctly.
Ok,
This, of course, would not work if the memory controller is misprogrammed
- which was the cause of failures.
Goood old discussion :)
Which way can memory controller be misprogrammed ? The part that concerns
us are positions of Video RAM, AGP and System Ram in Radeon address space.
http://bugzilla.kernel.org/show_bug.cgi?id=2754
--- Additional Comments From [EMAIL PROTECTED] 2005-06-04 21:18 ---
I've no ideas on this either, there should be nothing cpufreq should affect in
the dri/drm driver, I'm thinking the X server may be doing something bad and
XFree86 4.3
http://bugzilla.kernel.org/show_bug.cgi?id=2554
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http://bugzilla.kernel.org/show_bug.cgi?id=3294
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