Hi,
thanks a lot guys -- opengl works for gaming on my radeon9600m10 :)
.
I encountered a problem with rendertest_glitz_glx. The errormessage I
get is drmRadeonCmdBuffer: -22 (exiting). As far as I looked at the code
I guess its an overflow. So I did some debugging. From gdb output I read
that the texture is there but no address to write it to. Is this a known
error? I use xorg 7.0 with mesa and drm from cvs.
I had similar problem with xgl and evas_gl_x11_test from evas library.
This is my first bug report here, so please tell me if the form is not
correct.
Best Regards;
Hannes Janetzek
(gdb) bt
#0 0x1b90590d in memcpy () from /usr/lib/valgrind/vgpreload_memcheck.so
#1 0x1be0a26a in r300UploadRectSubImage (rmesa=0x1bd2a898,
t=0x247b8a70, texImage=0x247b90c0, x=0, y=0, width=320,
height=280) at r300_texmem.c:245
#2 0x1be0a5cc in uploadSubImage (rmesa=0x1bd2a898, t=0x247b8a70,
hwlevel=0, x=0, y=0, width=16, height=5600, face=0)
at r300_texmem.c:325
#3 0x1be0afa9 in r300UploadTexImages (rmesa=0x1bd2a898, t=0x247b8a70,
face=0) at r300_texmem.c:523
#4 0x1be0e81f in enable_tex_rect (ctx=0x1bd3c808, unit=0) at
r300_texstate.c:1059
#5 0x1be0e9e8 in r300UpdateTextureUnit (ctx=0x1bd3c808, unit=0) at
r300_texstate.c:1150
#6 0x1be0eb51 in r300UpdateTextureState (ctx=0x1bd3c808) at
r300_texstate.c:1182
#7 0x1be0561a in r300ResetHwState (r300=0x1bd2a898) at
r300_state.c:1805
#8 0x1be05447 in r300InvalidateState (ctx=0x1bd3c808,
new_state=8193635) at r300_state.c:1746
#9 0x1be7c969 in _mesa_update_state (ctx=0x1bd3c808) at state.c:1029
#10 0x1bf6a0e0 in _mesa_validate_DrawArrays (ctx=0x1bd3c808, mode=7,
start=0, count=4) at api_validate.c:226
#11 0x1bfadfc3 in _tnl_DrawArrays (mode=7, start=0, count=4) at
t_array_api.c:125
#12 0x1beacfe5 in neutral_DrawArrays (mode=7, start=0, count=4) at
vtxfmt_tmp.h:334
#13 0x1ba6d09c in glDrawArrays (mode=7, first=0, count=4) at
glapitemp.h:1635
#14 0x1bb0034c in glitz_geometry_draw_arrays (gl=0x1b9287a0,
dst=0x248baaa8, type=151, bounds=0x52bfdbc8, damage=5)
at glitz_geometry.c:388
#15 0x1baf5d92 in glitz_composite (op=151, src=0x247b88e8,
mask=0x52bfdc60, dst=0x248baaa8, x_src=0, y_src=0, x_mask=0,
y_mask=0, x_dst=0, y_dst=0, width=320, height=280) at glitz.c:316
#16 0x0804d64b in _glitz_render_composite (op=RENDER_OPERATOR_SRC,
src=0x1bce8920, mask=0x0, dst=0x52bfe600, x_src=0,
y_src=0, x_mask=0, y_mask=0, x_dst=0, y_dst=0, width=1388302079,
height=618475774) at glitz.c:53
#17 0x0804aabd in _render_set_background (surface=0x52bfe600,
grad=0x24dd30fe, logo=0x246bafd0) at rendertest.c:166
#18 0x0804b8bb in render_run (surface=0x52bfe600, settings=0x97) at
rendertest.c:705
#19 0x0804e3a6 in main (argc=151, argv=0x97) at glitz_glx.c:237
(gdb) fr 1
#1 0x1be0a26a in r300UploadRectSubImage (rmesa=0x1bd2a898,
t=0x247b8a70, texImage=0x247b90c0, x=0, y=0, width=320,
height=280) at r300_texmem.c:245
245 memcpy(region.address +
region.start, tex,
(gdb) l
240 fprintf(stderr,
241 "%s: src_pitch %d
dst_pitch %d\n",
242 __FUNCTION__, src_pitch,
dstPitch);
243
244 if (src_pitch == dstPitch) {
245 memcpy(region.address +
region.start, tex,
246 lines * src_pitch);
247 } else {
248 char *buf = region.address +
region.start;
249 int i;
(gdb) p tex
$1 = 0x24dc3200 "\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200
\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200
\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200
\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200
\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200
\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200
\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200
\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200
\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200
\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200
\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200
\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200
\uffff\200\200\200\uffff\200\200\200\uffff\200\200\200"...
(gdb) p region.address
$2 = 0x52bed000 <Address 0x52bed000 out of bounds>
(gdb) p region.start
$3 = 0
(gdb)
dmesg says :
PCI: Unable to reserve mem region #1:[EMAIL PROTECTED] for device
0000:01:00.0
could his cause the problem?
.
.
agpgart: Detected an Intel 855PM Chipset.
agpgart: AGP aperture is 128M @ 0xe0000000
ReiserFS: hda4: found reiserfs format "3.6" with standard journal
ReiserFS: hda4: using ordered data mode
ReiserFS: hda4: journal params: device hda4, size 8192, journal first
block 18, max trans len 1024, max batch 900, max commit age 30, max
trans age 30
ReiserFS: hda4: checking transaction log (hda4)
ReiserFS: hda4: replayed 1 transactions in 0 seconds
ReiserFS: hda4: Using r5 hash to sort names
Real Time Clock Driver v1.12
ACPI: PCI Interrupt 0000:00:1f.5[B] -> Link [LNKB] -> GSI 7 (level, low)
-> IRQ 7
PCI: Setting latency timer of device 0000:00:1f.5 to 64
intel8x0_measure_ac97_clock: measured 55470 usecs
intel8x0: clocking to 48000
cdrom: open failed.
[drm] Initialized drm 1.0.1 20051102
PCI: Unable to reserve mem region #1:[EMAIL PROTECTED] for device
0000:01:00.0
[drm] Initialized radeon 1.22.0 20060120 on minor 0:
[drm] Used old pci detect: framebuffer loaded
agpgart: Found an AGP 2.0 compliant device at 0000:00:00.0.
agpgart: Putting AGP V2 device at 0000:00:00.0 into 4x mode
agpgart: Putting AGP V2 device at 0000:01:00.0 into 4x mode
[drm] Loading R300 Microcode
ipw2200: Unknown notification: subtype=40,flags=0xa0,size=40
[drm:r300_emit_raw_packet3] *ERROR* Unknown packet3 header
(0xc0059b00)
[drm:r300_emit_packet3] *ERROR* r300_emit_raw_packet3 failed
[drm:r300_do_cp_cmdbuf] *ERROR* r300_emit_packet3 failed
[drm:r300_emit_raw_packet3] *ERROR* Unknown packet3 header (0xc0059b00)
[drm:r300_emit_packet3] *ERROR* r300_emit_raw_packet3 failed
[drm:r300_do_cp_cmdbuf] *ERROR* r300_emit_packet3 failed
.
.
The drm:r300... errors are thrown when I start rendertest_glitz_glx
cat /proc/mtrr
reg00: base=0x00000000 ( 0MB), size= 512MB: write-back, count=1 //
first memslot
reg01: base=0x20000000 ( 512MB), size= 256MB: write-back, count=1 //
second memslot
reg02: base=0xfeda0000 (4077MB), size= 128KB: write-through, count=1
reg03: base=0xd0000000 (3328MB), size= 64MB: write-combining,
count=1 // ??? I think the vesa-framebuffer
reg04: base=0xe0000000 (3584MB), size= 128MB: write-combining,
count=1 // graphics ram
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