memory leak in r8712_init_recv_priv

Hello, syzbot found the following issue on: HEAD commit:467f8165 Merge tag 'close-range-cloexec-unshare-v5.11' of .. git tree: upstream console output: https://syzkaller.appspot.com/x/log.txt?x=142b574550 kernel config: https://syzkaller.appspot.com/x/.config?x=37c889fb8b2761af

[PATCH v2] staging: rtl8192e: fix bool comparison in expressions

There are certain conditional expressions in rtl8192e, where a boolean variable is compared with true/false, in forms such as (foo == true) or (false != bar), which does not comply with checkpatch.pl (CHECK: BOOL_COMPARISON), according to which boolean variables should be themselves used in the

Re: [PATCH v2 41/48] memory: tegra20-emc: Use devm_tegra_core_dev_init_opp_table()

19.12.2020 14:02, Krzysztof Kozlowski пишет: > On Thu, Dec 17, 2020 at 09:06:31PM +0300, Dmitry Osipenko wrote: >> Use common devm_tegra_core_dev_init_opp_table() helper for the OPP table >> initialization. >> >> Signed-off-by: Dmitry Osipenko >> --- >> drivers/memory/tegra/tegra20-emc.c | 57

Re: [PATCH v2 07/48] dt-bindings: arm: tegra: Add binding for core power domain

19.12.2020 13:57, Krzysztof Kozlowski пишет: > On Thu, Dec 17, 2020 at 09:05:57PM +0300, Dmitry Osipenko wrote: >> All NVIDIA Tegra SoCs have a core power domain where majority of hardware >> blocks reside. Add binding for the core power domain. >> >> Signed-off-by: Dmitry Osipenko >> --- >>

Re: [PATCH] staging: rtl8192e: fix bool comparison in expressions

On Thu, Dec 17, 2020 at 05:12:04PM +0530, Aditya Srivastava wrote: > There are certain conditional expressions in rtl8192e, where a boolean > variable is compared with true/false, in forms such as (foo == true) or > (false != bar), which does not comply with checkpatch.pl (CHECK: >

Re: [PATCH 8455/8455] staging: rtl8188eu: core: fixed a comment format issue.

On Sat, Dec 19, 2020 at 02:43:12PM -0800, Daniel West wrote: > Fixed a checkpatch warning: > > WARNING: Block comments use * on subsequent lines > #4595: FILE: drivers/staging/rtl8188eu/core/rtw_mlme_ext.c:4595: > +/ > +

Re: [PATCH] staging: qlge: Removed duplicate word in comment.

On Fri, Dec 18, 2020 at 05:48:29PM -0800, Daniel West wrote: > This patch fixes the checkpatch warning: > > WARNING: Possible repeated word: 'and' > > Signed-off-by: Daniel West > --- > drivers/staging/qlge/qlge_main.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git

[PATCH v5 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f5eafee83bc6..f0c51d9760ec 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11247,6 +11247,12 @@ L:

[PATCH v5 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml' contains 'mediatek' as a valid vendor string. Some nodes in the device tree are using an invalid vendor string vfor 'mtk' instead. Fix all of them in dts file. Update also ralink mt7621 related code to properly match new

[PATCH v5 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h diff --git

[PATCH v5 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Signed-off-by: Sergio Paracuellos ---

[PATCH v5 3/6] clk: ralink: add clock driver for mt7621 SoC

The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and dividers used for CPU and some sort of BUS. * SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable clocks for all or

[PATCH v5 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Adds device tree binding documentation for clocks in the MT7621 SOC. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-clk.yaml | 52 +++ 1 file changed, 52 insertions(+) create mode 100644

[PATCH v5 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

This patchset ports CPU clock detection for MT7621 from OpenWrt and adds a complete clock plan for the mt7621 SOC. The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and