Rename ODM_PhyStatusQuery() to odm_phy_status_query() to avoid camel
case.
Signed-off-by: Michael Straube
---
drivers/staging/rtl8188eu/hal/odm_hwconfig.c | 6 +++---
drivers/staging/rtl8188eu/hal/rtl8188e_rxdesc.c | 4 ++--
drivers/staging/rtl8188eu/include/odm_hwconfig.h | 8
3 f
Rename parameters of odm_phy_status_query() to avoid camel case.
pDM_Odm -> dm_odm
pPhyInfo -> phy_info
pPhyStatus -> phy_status
pPktinfo -> pkt_info
Signed-off-by: Michael Straube
---
drivers/staging/rtl8188eu/hal/odm_hwconfig.c | 9 -
drivers/staging/rtl8188eu/include/odm_hwconfig
On Sat, Mar 06, 2021 at 12:38:17PM +0600, nabil5352 wrote:
> Fixed a struct without const
>
> Signed-off-by: nabil5352
> ---
> drivers/staging/android/ashmem.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/staging/android/ashmem.c
> b/drivers/staging/android/
Hi again,
On Sat, Mar 6, 2021 at 8:12 AM Sergio Paracuellos
wrote:
>
> Hi Rob,
>
> On Fri, Mar 5, 2021 at 11:47 PM Rob Herring wrote:
> [snip]
> > > +
> > > + ralink,sysctl:
> > > +$ref: /schemas/types.yaml#/definitions/phandle
> > > +description:
> > > + phandle of syscon used to
From: Zhang Yunkai
'ia_css_isys.h' included in 'sh_css.c' is duplicated.
It is also included in the 30th line.
Signed-off-by: Zhang Yunkai
---
drivers/staging/media/atomisp/pci/sh_css.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/staging/media/atomisp/pci/sh_css.c
b/drivers/
When arm_state is NULL, no error return code of vchiq_release_internal()
and vchiq_use_internal() is assigned.
To fix this bug, ret is assigned with VCHIQ_ERROR.
Reported-by: TOTE Robot
Signed-off-by: Jia-Ju Bai
---
.../staging/vc04_services/interface/vchiq_arm/vchiq_arm.c | 8 ++--
1 file
The device_reset() function is marked as "__must_check", thus the static
analysis tool "sparse" complains that in ralink-gdma its return value is
ignored. Log a warning in case it returns an error.
Signed-off-by: Giovanni Gherdovich
---
drivers/staging/ralink-gdma/ralink-gdma.c | 4 +++-
1 file
On Fri, Mar 05, 2021 at 08:55:09PM +0100, gabriele.mod...@gmail.com wrote:
> From: Gabriele Modena
>
> Fix style warnings reported by checkpatch.pl on op-rfkill.c
> by moving */ on a separate line in a block comment,
> adding a missing blank line after declarations,
> and reformatting a quoted st
On Wed, Feb 24, 2021 at 06:40:40PM +0530, Shubhrajyoti Datta wrote:
> Add the devicetree binding for the xilinx clocking wizard.
>
> Signed-off-by: Shubhrajyoti Datta
> ---
> v6:
> Fix a yaml warning
> v7:
> Add vendor prefix speed-grade
> v8:
> Fix the warnings
> v10:
> Add nr-outputs
>
Hi nabil5352,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on staging/staging-testing]
url:
https://github.com/0day-ci/linux/commits/nabil5352/Staging-android-ashmem-fixed-a-struct-without-const/20210307-103559
base: https://git.kernel.org/pub/scm/linux/kernel/
Hi,
On Sat, Mar 6, 2021 at 10:54 AM Sergio Paracuellos
wrote:
>
> Hi again,
>
> On Sat, Mar 6, 2021 at 8:12 AM Sergio Paracuellos
> wrote:
> >
> > Hi Rob,
> >
> > On Fri, Mar 5, 2021 at 11:47 PM Rob Herring wrote:
> > [snip]
> > > > +
> > > > + ralink,sysctl:
> > > > +$ref: /schemas/types.y
Adds device tree binding documentation for clocks in the
MT7621 SOC.
Signed-off-by: Sergio Paracuellos
---
.../bindings/clock/mediatek,mt7621-sysc.yaml | 68 +++
1 file changed, 68 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.ya
This patchset ports CPU clock detection for MT7621 from OpenWrt
and adds a complete clock plan for the mt7621 SOC.
The documentation for this SOC only talks about two registers
regarding to the clocks:
* SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped
refclock. PLL and dividers
Adds dt binding header for 'mediatek,mt7621-clk' clocks.
Acked-by: Rob Herring
Signed-off-by: Sergio Paracuellos
---
include/dt-bindings/clock/mt7621-clk.h | 41 ++
1 file changed, 41 insertions(+)
create mode 100644 include/dt-bindings/clock/mt7621-clk.h
diff --git a/
Clocks for SoC mt7621 have been properly integrated so there is
no need to declare fixed clocks at all in the device tree. Remove
all of them, add new device tree nodes for mt7621-clk and update
the rest of the nodes to use them.
Acked-by: Greg Kroah-Hartman
Signed-off-by: Sergio Paracuellos
---
The documentation for this SOC only talks about two
registers regarding to the clocks:
* SYSC_REG_CPLL_CLKCFG0 - provides some information about
boostrapped refclock. PLL and dividers used for CPU and some
sort of BUS.
* SYSC_REG_CPLL_CLKCFG1 - a banch of gates to enable/disable
clocks for all or s
Vendor listed for mediatek in kernel vendor file 'vendor-prefixes.yaml'
contains 'mediatek' as a valid vendor string. Some nodes in the device
tree are using an invalid vendor string vfor 'mtk' instead. Fix all of
them in dts file. Update also ralink mt7621 related code to properly
match new string
Adding myself as maintainer for mt7621 clock driver.
Signed-off-by: Sergio Paracuellos
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 809a68af5efd..be5ada6b4309 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11288,6 +11288,12 @@ L: l
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