-randconfig-c003-20210407
| |--
drivers-tty-tty_buffer.c:error:TTY_LOCK_SLAVE-undeclared-(first-use-in-this-function)
| `--
drivers-tty-tty_mutex.c:error:TTY_LOCK_SLAVE-undeclared-(first-use-in-this-function)
|-- arc-randconfig-r011-20210407
| |--
drivers-tty-tty_buffer.c:error:TTY_LOCK_SLAVE
allmodconfig
powerpc allnoconfig
i386 randconfig-a006-20210407
i386 randconfig-a003-20210407
i386 randconfig-a001-20210407
i386 randconfig-a004-20210407
i386 randconfig
ig
powerpc allyesconfig
powerpc allmodconfig
i386 randconfig-a006-20210407
i386 randconfig-a003-20210407
i386 randconfig-a001-20210407
i386 randconfig-a004-20210407
i386
tree: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git
tty-test
head: bb57c5de81c6feaad869acce7c38b1049115ac75
commit: bb57c5de81c6feaad869acce7c38b1049115ac75 [9/9] tty: move some internal
tty lock enums and functions out of tty.h
config: s390-randconfig-r032-20210407
-20210407 (attached as .config)
compiler: sparc64-linux-gcc (GCC) 9.3.0
reproduce:
wget
https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O
~/bin/make.cross
chmod +x ~/bin/make.cross
# apt-get install sparse
# sparse version: v0.6.3-279-g6d5d9b42
allyesconfig
sparc defconfig
i386defconfig
mips allmodconfig
i386 randconfig-a006-20210407
i386 randconfig-a003-20210407
i386 randconfig-a001-20210407
defconfig
i386defconfig
mips allyesconfig
mips allmodconfig
powerpc allyesconfig
powerpc allmodconfig
i386 randconfig-a006-20210407
Ulf Hansson writes:
>> If I follow what has been done in other drivers I would write something
>> like:
>>
>> static int wfx_sdio_suspend(struct device *dev)
>> {
>> struct sdio_func *func = dev_to_sdio_func(dev);
>> struct wfx_sdio_priv *bus = sdio_get_drvdata(func);
>>
Split the VPU node in two: one for G1 and one for G2 since they are
different hardware blocks.
Add syscon for the hardware control block.
Remove the reg-names property that is useless.
Each VPU node only needs one interrupt.
Change G2 assigned clock to match the specification.
In both nodes all
Add variant to IMX8M to enable G2/HEVC codec.
Define the capabilities for the hardware up to 3840x2160.
G2 doesn't have a postprocessor, uses the same clocks and has it
own interrupt.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Philipp Zabel
Reviewed-by: Ezequiel Garcia
---
version 9:
-
Implement all the logic to get G2 hardware decoding HEVC frames.
It supports up level 5.1 HEVC stream.
It doesn't support yet 10 bits formats or the scaling feature.
Add HANTRO HEVC dedicated control to skip some bits at the beginning
of the slice header. That is very specific to this hardware so
The HEVC HANTRO driver needs to know the number of bits to skip at
the beginning of the slice header.
That is a hardware specific requirement so create a dedicated control
for this purpose.
Signed-off-by: Benjamin Gaignard
---
version 9:
- Corrections in commit message.
- Move control
Make sure that V4L2_PIX_FMT_HEVC_SLICE is correctly handled by the driver.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
---
version 9:
- Corrections in commit message
version 8:
- Add Ezequiel review tag
drivers/staging/media/hantro/hantro_v4l2.c | 1 +
1 file changed, 1
If the variant doesn't support postprocessed formats make sure it will
be ok.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
---
version 9:
- Corrections in commit message
version 8:
- add Ezequiel review tag
drivers/staging/media/hantro/hantro.h | 8 ++--
Define which HEVC profiles (up to level 5.1) and features
(no scaling, no 10 bits) are supported by the driver.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
---
version 8:
- add Ezequiel review tag
drivers/staging/media/hantro/hantro.h | 3 ++
Add decode params control and the associated structure to group
all the information that are needed to decode a reference frame as
is described in ITU-T Rec. H.265 section "8.3.2 Decoding process
for reference picture set".
Adapt Cedrus driver to these changes.
Signed-off-by: Benjamin Gaignard
Change hantro_codec_ops run prototype from 'void' to 'int'.
This allows the driver to cancel the job if an error occurs while configuring
the hardware.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
---
version 9:
- Corrections in commit message
version 8:
- add Ezequiel
Add fields and flags as they are defined in
7.4.3.3.1 "General picture parameter set RBSP semantics of the
H.265 ITU specification.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
---
version 8:
- add Ezequiel review tag
.../userspace-api/media/v4l/ext-ctrls-codec.rst| 14
In order to be able to share the control hardware block between
VPUs use a syscon instead a ioremap it in the driver.
To keep the compatibility with older DT if 'nxp,imx8mq-vpu-ctrl'
phandle is not found look at 'ctrl' reg-name.
With the method it becomes useless to provide a list of register
The IMX8MQ got two VPUs but until now only G1 has been enabled.
This series aim to add the second VPU (aka G2) and provide basic
HEVC decoding support.
To be able to decode HEVC it is needed to add/update some of the
structures in the uapi. In addition of them one HANTRO dedicated
control is
Introducing the G2 hevc video decoder requires modifications of the bindings to
allow
one node per VPU.
VPUs share one hardware control block which is provided as a phandle on
a syscon.
Each node has now one reg and one interrupt.
Add a compatible for G2 hardware block: nxp,imx8mq-vpu-g2.
To be
Add 'nxp,imx8mq-vpu-ctrl' to the list of possible syscon.
It will used to access the VPU control registers.
Signed-off-by: Benjamin Gaignard
Acked-by: Rob Herring
Acked-by: Lee Jones
---
version 9:
- corrections in commit message
version 8:
- Add Lee ack
version 7:
- Add Rob ack
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