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Good day
How are you today, did you receive the email I sent you three days ago? For
important discussion on ( Investment ) If not please reply me back so that I
will resend it again.
Please confirm if you did ( posteaz...@gmail.com ).
Best Regards,
Mr. Fred Grenville
Add variant to IMX8M to enable G2/HEVC codec.
Define the capabilities for the hardware up to 3840x2160.
G2 doesn't have a postprocessor, uses the same clocks and has it
own interrupt.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Philipp Zabel
Reviewed-by: Ezequiel Garcia
---
Implement all the logic to get G2 hardware decoding HEVC frames.
It supports up level 5.1 HEVC stream.
It doesn't support yet 10 bits formats or the scaling feature.
Add HANTRO HEVC dedicated control to skip some bits at the beginning
of the slice header. That is very specific to this hardware so
Make sure that V4L2_PIX_FMT_HEVC_SLICE is correctly handled by the driver.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
---
drivers/staging/media/hantro/hantro_v4l2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/staging/media/hantro/hantro_v4l2.c
The HEVC HANTRO driver needs to know the number of bits to skip at
the beginning of the slice header.
That is a hardware specific requirement so create a dedicated control
for this purpose.
Signed-off-by: Benjamin Gaignard
---
.../userspace-api/media/drivers/hantro.rst| 19
If the variant doesn't support postprocessed formats make sure it will
be ok.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
---
drivers/staging/media/hantro/hantro.h | 8 ++--
drivers/staging/media/hantro/hantro_postproc.c | 14 ++
Define which HEVC profiles (up to level 5.1) and features
(no scaling, no 10 bits) are supported by the driver.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
---
drivers/staging/media/hantro/hantro.h | 3 ++
drivers/staging/media/hantro/hantro_drv.c | 58
Change hantro_codec_ops run prototype from 'void' to 'int'.
This allows the driver to cancel the job if an error occurs while configuring
the hardware.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
---
drivers/staging/media/hantro/hantro_drv.c | 4 +++-
Add decode params control and the associated structure to group
all the information that are needed to decode a reference frame as
is described in ITU-T Rec. H.265 section "8.3.2 Decoding process
for reference picture set".
Adapt Cedrus driver to these changes.
Signed-off-by: Benjamin Gaignard
Add fields and flags as they are defined in
7.4.3.3.1 "General picture parameter set RBSP semantics of the
H.265 ITU specification.
Signed-off-by: Benjamin Gaignard
Reviewed-by: Ezequiel Garcia
---
.../userspace-api/media/v4l/ext-ctrls-codec.rst| 14 ++
The IMX8MQ got two VPUs but until now only G1 has been enabled.
This series aim to add the second VPU (aka G2) and provide basic
HEVC decoding support.
To be able to decode HEVC it is needed to add/update some of the
structures in the uapi. In addition of them one HANTRO dedicated
control is
Hi Ashish,
On 18/04/2021 03:26, Ashish Kalra wrote:
> On Sat, Apr 17, 2021 at 08:56:13PM +0200, Mauro Carvalho Chehab wrote:
>> Em Sat, 17 Apr 2021 21:06:27 +0530
>> Ashish Kalra escreveu:
>>
>>> Upon running sparse, "warning: dubious: !x | !y" is brought to notice
>>> for this file. Logical
On 20/04/2021 11:31, Benjamin Gaignard wrote:
>
> Le 20/04/2021 à 11:16, Hans Verkuil a écrit :
>> On 20/04/2021 11:10, Benjamin Gaignard wrote:
>>> Le 16/04/2021 à 17:14, Lucas Stach a écrit :
Am Freitag, dem 16.04.2021 um 15:08 +0200 schrieb Benjamin Gaignard:
> Le 16/04/2021 à 12:54,
On Sat, Apr 17, 2021 at 09:31:32PM +, David Laight wrote:
> From: Mauro Carvalho Chehab
> > Sent: 17 April 2021 19:56
> >
> > Em Sat, 17 Apr 2021 21:06:27 +0530
> > Ashish Kalra escreveu:
> >
> > > Upon running sparse, "warning: dubious: !x | !y" is brought to notice
> > > for this file.
From: Dan Carpenter
> Sent: 20 April 2021 11:28
>
> On Sat, Apr 17, 2021 at 09:31:32PM +, David Laight wrote:
> > From: Mauro Carvalho Chehab
> > > Sent: 17 April 2021 19:56
> > >
> > > Em Sat, 17 Apr 2021 21:06:27 +0530
> > > Ashish Kalra escreveu:
> > >
> > > > Upon running sparse,
Le 20/04/2021 à 11:16, Hans Verkuil a écrit :
On 20/04/2021 11:10, Benjamin Gaignard wrote:
Le 16/04/2021 à 17:14, Lucas Stach a écrit :
Am Freitag, dem 16.04.2021 um 15:08 +0200 schrieb Benjamin Gaignard:
Le 16/04/2021 à 12:54, Lucas Stach a écrit :
Am Mittwoch, dem 07.04.2021 um 09:35
On 20/04/2021 11:10, Benjamin Gaignard wrote:
>
> Le 16/04/2021 à 17:14, Lucas Stach a écrit :
>> Am Freitag, dem 16.04.2021 um 15:08 +0200 schrieb Benjamin Gaignard:
>>> Le 16/04/2021 à 12:54, Lucas Stach a écrit :
Am Mittwoch, dem 07.04.2021 um 09:35 +0200 schrieb Benjamin Gaignard:
>
Le 16/04/2021 à 17:14, Lucas Stach a écrit :
Am Freitag, dem 16.04.2021 um 15:08 +0200 schrieb Benjamin Gaignard:
Le 16/04/2021 à 12:54, Lucas Stach a écrit :
Am Mittwoch, dem 07.04.2021 um 09:35 +0200 schrieb Benjamin Gaignard:
In order to be able to share the control hardware block between
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