From: Chen-Yu Tsai
The custom regulatory ruleset in the rtl8723bs driver lists an incorrect
number of rules: one too many. This results in an out-of-bounds access,
as detected by KASAN. This was possible thanks to the newly added support
for KASAN on ARMv7.
Fix this by filling in the correct
On Fri, Dec 4, 2020 at 12:25 AM Martin Cerveny wrote:
>
> Hello.
>
> On Thu, 3 Dec 2020, Chen-Yu Tsai wrote:
>
> > Hi,
> >
> > On Mon, Nov 16, 2020 at 8:57 PM Martin Cerveny
> > wrote:
> >>
> >> Allwinner V3s has system control and SRAM
Hi,
On Mon, Nov 16, 2020 at 8:57 PM Martin Cerveny wrote:
>
> Allwinner V3s has system control and SRAM C1 region similar to H3.
>
> Signed-off-by: Martin Cerveny
> ---
> arch/arm/boot/dts/sun8i-v3s.dtsi | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm/boot/dts/
On Mon, Nov 16, 2020 at 8:58 PM Martin Cerveny wrote:
>
> Allwinner V3S SoC has a video engine.
> Add a node for it.
>
> Signed-off-by: Martin Cerveny
Acked-by: Chen-Yu Tsai
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On Mon, Nov 16, 2020 at 8:58 PM Martin Cerveny wrote:
>
> Allwinner V3s SoC contains video engine. Add compatible for it.
>
> Signed-off-by: Martin Cerveny
Acked-by: Chen-Yu Tsai
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ve the MBUS quirks
> media: cedrus: Remove the MBUS quirks
> media: sun8i-di: Remove the call to of_dma_configure
Whole series looks good to me.
Reviewed-by: Chen-Yu Tsai
Now the question remaining is how do we merge this series so that
the notifier gets merged before all the code dea
On Wed, Dec 5, 2018 at 5:48 PM Paul Kocialkowski
wrote:
>
> Hi,
>
> On Wed, 2018-12-05 at 17:45 +0800, Chen-Yu Tsai wrote:
> > On Wed, Dec 5, 2018 at 5:25 PM Paul Kocialkowski
> > wrote:
> > > Add the H5-specific system control node description to its device-tre
Add device-tree compatible and variant for A64 support
> arm64: dts: allwinner: h5: Add Video Engine node
> arm64: dts: allwinner: a64: Add Video Engine node
Other than the error in patch 7,
Acked-by: Chen-Yu Tsai
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On Wed, Dec 5, 2018 at 5:25 PM Paul Kocialkowski
wrote:
>
> Add the H5-specific system control node description to its device-tree
> with support for the SRAM C1 section, that will be used by the video
> codec node later on.
>
> The CPU-side SRAM address was obtained empirically while the size was
On Fri, Nov 16, 2018 at 12:52 AM Chen-Yu Tsai wrote:
>
> On Thu, Nov 15, 2018 at 10:50 PM Paul Kocialkowski
> wrote:
> >
> > Add the H5-specific system control node description to its device-tree
> > with support for the SRAM C1 section, that will be used by the vi
On Fri, Nov 16, 2018 at 5:39 PM Maxime Ripard wrote:
>
> On Thu, Nov 15, 2018 at 03:50:06PM +0100, Paul Kocialkowski wrote:
> > Now that we have specific nodes for the H3 and H5 system-controller
> > that allow proper access to the EMAC clock configuration register,
> > we no longer need a common
On Thu, Nov 15, 2018 at 10:50 PM Paul Kocialkowski
wrote:
>
> Add the H5-specific system control node description to its device-tree
> with support for the SRAM C1 section, that will be used by the video
> codec node later on.
>
> Signed-off-by: Paul Kocialkowski
> ---
> arch/arm64/boot/dts/allw
On Thu, Nov 15, 2018 at 10:50 PM Paul Kocialkowski
wrote:
>
> Add the description for the SRAM C1 section to the A64 device-tree.
>
> Signed-off-by: Paul Kocialkowski
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 14 ++
> 1 file changed, 14 insertions(+)
>
> diff --git a/ar
ic binding for the syscon node
> attached to the EMAC instead of the generic syscon binding.
>
> Signed-off-by: Paul Kocialkowski
Reviewed-by: Chen-Yu Tsai
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> that range.
>
> Extend the register size to its full range (0x1000) as a result.
>
> Signed-off-by: Paul Kocialkowski
Other than the subject format,
Acked-by: Chen-Yu Tsai
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On Thu, Nov 15, 2018 at 10:50 PM Paul Kocialkowski
wrote:
>
> This cosmetic change removes the heading 0 in the video-codec unit
> address, as it's done for other nodes.
>
> Signed-off-by: Paul Kocialkowski
Other than the subject format we can fix when applying,
Ac
uot;,
or "sun8i: a33:" in this case. This format seems to be used more often
than your alternative format.
I can fix it up when applying.
Acked-by: Chen-Yu Tsai
ChenYu
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On Thu, Nov 15, 2018 at 10:51 PM Paul Kocialkowski
wrote:
>
> This adds nodes for the Video Engine and the associated reserved memory
> for the H5. Up to 96 MiB of memory are dedicated to the CMA pool.
>
> The pool is located at the end of the first 256 MiB of RAM so that the
> VPU can access it.
On Sat, Sep 8, 2018 at 6:06 PM Hans Verkuil wrote:
>
> On 09/07/2018 06:33 PM, Paul Kocialkowski wrote:
> > This brings the requested modifications on top of version 9 of the
> > Cedrus VPU driver, that implements stateless video decoding using the
> > Request API.
> >
> > Paul Kocialkowski (2):
>
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