d 500MHz clock or a clock created by the memory controller.
sysctl contains a bootstrap register to determine crystal clock, a
clock mux for choosing between the 3 sources for CPU clock, and
a clock gate register for various peripherals. The ralink,memctl
phandle here is to read the cpu clock freque
k design of mt7621 doesn't seem
to be part of ralink legacy stuff, and ralink is already
acquired by mediatek anyway.
I think it should be put in drivers/clk/mediatek instead.
--
Regards,
Chuanhong Guo
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ing auto
clock gating.
--
Regards,
Chuanhong Guo
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On Thu, Nov 12, 2020 at 9:26 AM Chuanhong Guo wrote:
>
> I've already said in previous threads that clock assignment in
> current linux kernel is not trustworthy.
> I've got the clock plan for mt7621 now. (Can't share it, sorry.)
> Most of your clock assumptions abov
; - "pcie0": "ahb"
> - "pcie1": "ahb"
> - "pcie2": "ahb"
> - "crypto": "ahb"
> - "shxc": "ahb"
>
> There was a previous attempt of doing this here[0] but th
ck {
> > &pcie {
> > pinctrl-names = "default";
> > pinctrl-0 = <&pcie_pins>;
> > +
> > + reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>,
> > + <&gp
rds can't be detected on a specific
board without gpio7 and/or gpio8, override gpio-resets in dts of
that board.
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Chuanhong Guo
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e also in driver error path.
This pin conflict comes from incorrectly occupying pins that are not
used by pcie,
and should be fixed by not occupying those pins in the first place.
Releasing all
gpios isn't the proper way to go.
--
Regards,
Chuanhong Guo
___
On Tue, Feb 4, 2020 at 6:37 PM Dan Carpenter wrote:
>
> On Tue, Feb 04, 2020 at 05:59:21PM +0800, Chuanhong Guo wrote:
> > Hi!
> >
> > On Tue, Feb 4, 2020 at 5:47 PM Dan Carpenter
> > wrote:
> > >
> > > Please use ./scripts/get_maintainer.pl
should be
corrected.
Regards,
Chuanhong Guo
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There are 3 uarts on mt7621. This patch adds device tree node for
2nd and 2rd ones.
Signed-off-by: Chuanhong Guo
---
drivers/staging/mt7621-dts/mt7621.dtsi | 38 ++
1 file changed, 38 insertions(+)
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi
b/drivers/staging
The memc node from mt7621.dtsi has incorrect register resource.
Fix it according to the programming guide.
Signed-off-by: Weijie Gao
Signed-off-by: Chuanhong Guo
---
drivers/staging/mt7621-dts/mt7621.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging
ade my
> > point. Of course I can't read through the ancient and heavily hacked
> > vendor kernel to figure out a clock plan myself.
>
> Ok, I provided you some productive technical hints how it should be
> done. I don't think m
On Sun, Aug 18, 2019 at 4:26 PM Chuanhong Guo wrote:
>
> Hi!
>
> On Sun, Aug 18, 2019 at 3:59 PM Oleksij Rempel wrote:
> >
> > Am 18.08.19 um 09:19 schrieb Chuanhong Guo:
> > > Hi!
> > >
> > > On Sun, Aug 18, 2019 at 2:10 PM Oleksij Rempel
&
Hi!
On Sun, Aug 18, 2019 at 3:59 PM Oleksij Rempel wrote:
>
> Am 18.08.19 um 09:19 schrieb Chuanhong Guo:
> > Hi!
> >
> > On Sun, Aug 18, 2019 at 2:10 PM Oleksij Rempel
> > wrote:
> >>
> >>>> We have at least 2 know registers:
> >&g
Clock gate is an unrelated part and there is no information to
properly implement it unless MTK decided to release a clock plan
somehow.
> This code is currently on prototyping phase
Code for clock calculation is done, not "prototyping".
> It means, we cannot expect that this
hardcoded clocks. With this driver will work part of power
> management and nice devicetree without fixed clocks.
Regards,
Chuanhong Guo
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ks are there since this piece
of info is missing in datasheet.
>
> IMO - this information is enough to create full blown
> drivers/clk/mediatek/clk-mt7621.c
And this information isn't enough because the assumption above is incorrect :P
Regards,
Chuanhong Guo
an't determine corresponding clock frequencies for every
peripherals, thus unable to write a working clock driver.
>
> > +
> > + #clock-cells = <1>;
> > + clock-output-names = "cpu", "bus";
> >
This commit adds device-tree node for mt7621-pll and use its clocks
accordingly.
Signed-off-by: Chuanhong Guo
---
Changes since v1:
1. drop cpuclock node in gbpc1.dts
2. drop syscon in mt7621-pll node
drivers/staging/mt7621-dts/gbpc1.dts | 5 -
drivers/staging/mt7621-dts/mt7621.dtsi
: Weijie Gao
Signed-off-by: Chuanhong Guo
---
Changes since v1:
1. split patch.
2. calculate clocks using the function called by CLK_OF_DECLARE
drop direct function call in timer-gic.c of ralink_clk_init
3. drop assignment of mips-hpt-frequency
arch/mips/include/asm/mach-ralink/mt7621.h | 20
This commit adds device tree binding documentation for MT7621
PLL controller.
Signed-off-by: Chuanhong Guo
---
Change since v1:
drop useless syscon in compatible string
.../bindings/clock/mediatek,mt7621-pll.txt | 18 ++
1 file changed, 18 insertions(+)
create mode 100644
The memc node from mt7621.dtsi has incorrect register resource.
Fix it according to the programming guide.
Signed-off-by: Weijie Gao
Signed-off-by: Chuanhong Guo
---
Change since v1: None.
drivers/staging/mt7621-dts/mt7621.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
l and used it in mt7621-dts at
drivers/staging.
Changes since v1:
1. changed commit title prefix for dt include
2. split the patch adding clock node (details in that patch body)
3. drop useless syscon in dt documentation
4. drop cpuclock node for gbpc1
Chuanhong Guo (6):
dt-bindings: clock: a
This function isn't called anywhere. just drop it.
Signed-off-by: Chuanhong Guo
---
Change since v1:
New patch. Split from:
"MIPS: ralink: fix cpu clock of mt7621 and add dt clk devices"
arch/mips/ralink/mt7621.c | 43 ---
1 file change
This patch adds dt binding header for mediatek,mt7621-pll
Signed-off-by: Weijie Gao
Signed-off-by: Chuanhong Guo
Reviewed-by: Rob Herring
---
Change since v1:
Change commit title prefix.
include/dt-bindings/clock/mt7621-clk.h | 14 ++
1 file changed, 14 insertions(+)
create mode
On Wed, Jul 10, 2019 at 2:22 AM Chuanhong Guo wrote:
>
> This commit adds device-tree node for mt7621-pll and use its clock
> accordingly.
>
> Signed-off-by: Chuanhong Guo
Oops. Please ignore this single patch for now. I forgot to drop
cpuclock node in drivers/staging/mt7621-dts
The memc node from mt7621.dtsi has incorrect register resource.
Fix it according to the programming guide.
Signed-off-by: Weijie Gao
Signed-off-by: Chuanhong Guo
---
drivers/staging/mt7621-dts/mt7621.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging
This commit adds device tree binding documentation for MT7621
PLL controller.
Signed-off-by: Chuanhong Guo
---
.../bindings/clock/mediatek,mt7621-pll.txt| 19 +++
1 file changed, 19 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/mediatek,mt7621
Signed-off-by: Weijie Gao
Signed-off-by: Chuanhong Guo
---
arch/mips/include/asm/mach-ralink/mt7621.h | 20
arch/mips/ralink/mt7621.c | 102 ++---
arch/mips/ralink/timer-gic.c | 4 +-
3 files changed, 93 insertions(+), 33 deletions(-)
diff
This commit adds device-tree node for mt7621-pll and use its clock
accordingly.
Signed-off-by: Chuanhong Guo
---
drivers/staging/mt7621-dts/mt7621.dtsi | 15 +++
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi
b/drivers/staging
l and used it in mt7621-dts at
drivers/staging.
BTW: What should I do with such a patchset that touches multiple
parts in kernel?
Is it correct to send the entire patchset to lists of all involved
subsystems?
Chuanhong Guo (5):
MIPS: ralink: add dt binding header for mt7621-pll
MIPS: ralink: fi
This patch adds dt binding header for mediatek,mt7621-pll
Signed-off-by: Weijie Gao
Signed-off-by: Chuanhong Guo
Reviewed-by: Rob Herring
---
include/dt-bindings/clock/mt7621-clk.h | 14 ++
1 file changed, 14 insertions(+)
create mode 100644 include/dt-bindings/clock/mt7621-clk.h
pidev_to_mt7621_spi(spi);
>
> if ((spi->max_speed_hz == 0) ||
> - (spi->max_speed_hz > (rs->sys_freq / 2)))
> + (spi->max_speed_hz > (rs->sys_freq / 2)))
> spi->max_speed_hz = (rs->sys_freq
n fixed by my two "drop broken spi modes" patches.
>
> John: do you have any more details of the problem other than what is in
> the commit message?
>
> Thanks,
> NeilBrown
Regards,
Chuanhong Guo
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Hi!
On Wed, Mar 13, 2019 at 8:28 PM Matthias Brugger wrote:
>
>
>
> On 13/03/2019 13:24, Armando Miraglia wrote:
> [...]
> Apart from fixing styling issues it would be usefull to see if we can add
> support for mt7621 to drivers/spi/spi-mt65xx.c
It's impossible. They are completely different IPs.
RT2880_SPI_MODE_BITS macro because we now have only
SPI_LSB_FIRST implemented and the mode_bits is so short that we
don't need a macro there.
Signed-off-by: Chuanhong Guo
---
Change since v2:
fixed the following checkpatch.pl complaining:
CHECK: Please don't use multiple blank lines
#45: FIL
checkpatch.pl
Chuanhong Guo (2):
staging: mt7621-spi: drop the broken full-duplex mode
staging: mt7621-spi: drop support for SPI mode 1/2/3
drivers/staging/mt7621-spi/spi-mt7621.c | 147
1 file changed, 24 insertions(+), 123 deletions(-)
--
2.19.1
-duplex
mode is broken.
This piece of code also make CS1 unavailable since it forces the
broken full-duplex mode to be used on CS1.
Signed-off-by: Chuanhong Guo
---
Change since v2:
fixed the following checkpatch.pl complaining:
ERROR: space required before the open parenthesis '('
#82: FIL
Chuanhong Guo 于2018年12月6日周四 下午7:19写道:
>
> As explained in previous patch, this SPI controller seems to be
> tested on SPI flash only before mass production and some bits are
> swizzled under other SPI modes probably due to incorrect wiring
> inside the silicon. Drop implementation
Chuanhong Guo 于2018年12月6日周四 下午7:19写道:
>
> According to John Crispin (aka blogic) on IRC on Nov 26 2018:
> so basically i made cs1 work for MTK/labs when i built
> the linkit smart for them. the req-sheet said that cs1 should be proper
> duplex spi. however
>1) th
RT2880_SPI_MODE_BITS macro because we now have only
SPI_LSB_FIRST implemented and the mode_bits is so short that we
don't need a macro there.
Signed-off-by: Chuanhong Guo
---
Changes since v1:
drop unspoorted modes from mode_bits instead of reject them
in mt7621_spi_prepare.
dropped RT2880_SPI_MODES
-duplex
mode is broken.
This piece of code also make CS1 unavailable since it forces the
broken full-duplex mode to be used on CS1.
Signed-off-by: Chuanhong Guo
---
Changes since v1:
Quoted John's reply in commit message
slightly modified code comment
drivers/staging/mt7621-spi/spi-mt7621.c
forgot to reply to mailing list...
NeilBrown 于2018年12月5日周三 上午8:06写道:
>
> On Tue, Dec 04 2018, Chuanhong Guo wrote:
>
> > Hi!
> > NeilBrown 于2018年12月4日周二 上午5:55写道:
> >>
> >> On Mon, Dec 03 2018, Chuanhong Guo wrote:
> >>
> >> > Under M
Hi!
NeilBrown 于2018年12月4日周二 上午5:55写道:
>
> On Mon, Dec 03 2018, Chuanhong Guo wrote:
>
> > Under MORE_BUF_MODE the controller will always shift one bit out of
> > spi_opcode if (mosi_bit_cnt > 0) && (cmd_bit_cnt == 0) so the full-
> > duplex mode is broken
This SPI controller seems to be tested on SPI flash only before mass
production and some bits are swizzled under other SPI modes probably
due to incorrect wiring inside the silicon. Reject all modes except
mode0 because they are broken.
Signed-off-by: Chuanhong Guo
---
drivers/staging/mt7621
orces the
broken full-duplex mode to be enabled on CS1.
Signed-off-by: Chuanhong Guo
---
drivers/staging/mt7621-spi/spi-mt7621.c | 120 +++-
1 file changed, 15 insertions(+), 105 deletions(-)
diff --git a/drivers/staging/mt7621-spi/spi-mt7621.c
b/drivers/staging/mt7621-spi/sp
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