28.04.2021 17:51, Mauro Carvalho Chehab пишет:
> @@ -1069,11 +1071,17 @@ static int tegra_vde_probe(struct platform_device
> *pdev)
>* power-cycle it in order to put hardware into a predictable lower
>* power state.
>*/
> - pm_runtime_get_sync(dev);
> + if (pm_runti
29.04.2021 13:18, Mauro Carvalho Chehab пишет:
>> This is perfectly alright. Take a look at ov7740_remove() for example:
>>
>> pm_runtime_get_sync(&client->dev);
>> pm_runtime_disable(&client->dev);
>> pm_runtime_set_suspended(&client->dev);
>> pm_runtime_put_noidle(&client->dev
28.04.2021 10:20, Mauro Carvalho Chehab пишет:
> Em Tue, 27 Apr 2021 14:47:01 +0300
> Dmitry Osipenko escreveu:
>
>> 27.04.2021 13:26, Mauro Carvalho Chehab пишет:
>>> @@ -1088,8 +1090,9 @@ static int tegra_vde_remove(struct platform_device
>>> *pdev)
>
27.04.2021 13:26, Mauro Carvalho Chehab пишет:
> @@ -1088,8 +1090,9 @@ static int tegra_vde_remove(struct platform_device
> *pdev)
> {
> struct tegra_vde *vde = platform_get_drvdata(pdev);
> struct device *dev = &pdev->dev;
> + int ret;
>
> - pm_runtime_get_sync(dev);
> +
24.04.2021 09:44, Mauro Carvalho Chehab пишет:
> Commit dd8088d5a896 ("PM: runtime: Add pm_runtime_resume_and_get to deal with
> usage counter")
> added pm_runtime_resume_and_get() in order to automatically handle
> dev->power.usage_count decrement on errors.
>
> Use the new API, in order to clea
05.01.2021 20:11, Krzysztof Kozlowski пишет:
> On Thu, Dec 17, 2020 at 09:05:50PM +0300, Dmitry Osipenko wrote:
>> Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs, which reduces
>> power consumption and heating of the Tegra chips. Tegra SoC has multiple
>> hardware
17.12.2020 21:06, Dmitry Osipenko пишет:
> The GR3D1 hardware unit needs to pulse hardware reset after removing power
> clamp, otherwise reset won't be deasserted. Hence give reset a pulse after
> removing the clamp. This stayed unnoticed previously because power
> management wa
30.12.2020 07:46, Viresh Kumar пишет:
> On 28-12-20, 17:03, Dmitry Osipenko wrote:
>> 28.12.2020 09:22, Viresh Kumar пишет:
>>> On 24-12-20, 16:00, Dmitry Osipenko wrote:
>>>> In a device driver I want to set PD to the lowest performance state by
>>&
28.12.2020 09:22, Viresh Kumar пишет:
> On 24-12-20, 16:00, Dmitry Osipenko wrote:
>> In a device driver I want to set PD to the lowest performance state by
>> removing the performance vote when dev_pm_opp_set_rate(dev, 0) is
>> invoked by the driver.
>>
>> The O
24.12.2020 09:43, Viresh Kumar пишет:
> On 23-12-20, 23:37, Dmitry Osipenko wrote:
>> 23.12.2020 07:19, Viresh Kumar пишет:
>>> On 22-12-20, 22:15, Dmitry Osipenko wrote:
>>>> 22.12.2020 09:42, Viresh Kumar пишет:
>>>>> On 17-12-20, 21:06, Dmitry Osi
24.12.2020 07:10, Viresh Kumar пишет:
> On 23-12-20, 23:38, Dmitry Osipenko wrote:
>> Well, there is no "same structure", the opp_table->set_opp_data is NULL
>> there.
>
> Right, I saw that yesterday. What I meant was that we need to start allocating
> the
24.12.2020 09:51, Viresh Kumar пишет:
> On 23-12-20, 23:37, Dmitry Osipenko wrote:
>> 23.12.2020 08:57, Viresh Kumar пишет:
>>> What's wrong with getting the regulator in the driver as well ? Apart from
>>> the
>>> OPP core ?
>>
>> The volta
24.12.2020 09:28, Viresh Kumar пишет:
> On 23-12-20, 23:36, Dmitry Osipenko wrote:
>> 23.12.2020 07:34, Viresh Kumar пишет:
>>> On 22-12-20, 22:19, Dmitry Osipenko wrote:
>>>> 22.12.2020 12:12, Viresh Kumar пишет:
>>>>> rate will be 0 for both th
23.12.2020 23:37, Dmitry Osipenko пишет:
> 23.12.2020 08:57, Viresh Kumar пишет:
>> On 22-12-20, 22:39, Dmitry Osipenko wrote:
>>> 22.12.2020 22:21, Dmitry Osipenko пишет:
>>>>>> +if (IS_ERR(opp)) {
>>>>>> +dev_err(&
23.12.2020 07:22, Viresh Kumar пишет:
> On 22-12-20, 22:17, Dmitry Osipenko wrote:
>> 22.12.2020 11:59, Viresh Kumar пишет:
>>> On 17-12-20, 21:06, Dmitry Osipenko wrote:
>>>> A required OPP may not be available, and thus, all OPPs which are using
>>>> t
23.12.2020 09:01, Viresh Kumar пишет:
> On 17-12-20, 21:06, Dmitry Osipenko wrote:
>> Support set_opp() customization without requiring to use regulators. This
>> is needed by drivers which want to use dev_pm_opp_set_rate() for changing
>> rates of a multiple clocks an
23.12.2020 07:19, Viresh Kumar пишет:
> On 22-12-20, 22:15, Dmitry Osipenko wrote:
>> 22.12.2020 09:42, Viresh Kumar пишет:
>>> On 17-12-20, 21:06, Dmitry Osipenko wrote:
>>>> Add a ceil version of the dev_pm_opp_find_level(). It's handy to have if
>>>
23.12.2020 08:57, Viresh Kumar пишет:
> On 22-12-20, 22:39, Dmitry Osipenko wrote:
>> 22.12.2020 22:21, Dmitry Osipenko пишет:
>>>>> + if (IS_ERR(opp)) {
>>>>> + dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n",
>
23.12.2020 07:34, Viresh Kumar пишет:
> On 22-12-20, 22:19, Dmitry Osipenko wrote:
>> 22.12.2020 12:12, Viresh Kumar пишет:
>>> On 17-12-20, 21:06, Dmitry Osipenko wrote:
>>>> Fix adding OPP entries in a wrong (opposite) order if OPP rate is
>>>> unav
22.12.2020 22:21, Dmitry Osipenko пишет:
>>> + if (IS_ERR(opp)) {
>>> + dev_err(&genpd->dev, "failed to find OPP for level %u: %pe\n",
>>> + level, opp);
>>> + return PTR_ERR(opp);
>>> +
22.12.2020 12:14, Viresh Kumar пишет:
> On 17-12-20, 21:06, Dmitry Osipenko wrote:
>> diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi
>> b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi
>> index cbe84d25e726..983db1a06682 100644
>> --- a/arch/arm/boot/dts/t
22.12.2020 08:47, Viresh Kumar пишет:
> On 17-12-20, 21:06, Dmitry Osipenko wrote:
>> diff --git a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi
>> b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi
>> index b84afecea154..7e015cdfbc55 100644
>> --- a/arch/arm/boot/dts/t
22.12.2020 09:40, Viresh Kumar пишет:
> On 17-12-20, 21:06, Dmitry Osipenko wrote:
>> +++ b/drivers/soc/tegra/core-power-domain.c
>> @@ -0,0 +1,125 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * NVIDIA Tegra SoC Core Power Domain Driver
>&g
22.12.2020 12:12, Viresh Kumar пишет:
> On 17-12-20, 21:06, Dmitry Osipenko wrote:
>> Fix adding OPP entries in a wrong (opposite) order if OPP rate is
>> unavailable. The OPP comparison is erroneously skipped if OPP rate is
>> missing, thus OPPs are left unsorted.
>&g
22.12.2020 12:01, Viresh Kumar пишет:
> On 17-12-20, 21:06, Dmitry Osipenko wrote:
>> Support set_opp() customization without requiring to use regulators. This
>> is needed by drivers which want to use dev_pm_opp_set_rate() for changing
>> rates of a multiple clocks an
22.12.2020 11:59, Viresh Kumar пишет:
> On 17-12-20, 21:06, Dmitry Osipenko wrote:
>> A required OPP may not be available, and thus, all OPPs which are using
>> this required OPP should be unavailable too.
>>
>> Signed-off-by: Dmitry Osipenko
>> ---
>> dr
22.12.2020 01:54, Rob Herring пишет:
> On Thu, Dec 17, 2020 at 09:05:52PM +0300, Dmitry Osipenko wrote:
>> Power domain fits much better than a voltage regulator in regards to
>> a proper hardware description and from a software perspective as well.
>> Hence replace the co
22.12.2020 03:14, Rob Herring пишет:
> On Thu, Dec 17, 2020 at 09:05:56PM +0300, Dmitry Osipenko wrote:
>> Document "clocks" sub-node which describes Tegra SoC clocks that require
>> a higher voltage of the core power domain in order to operate properly on
>> a highe
22.12.2020 09:42, Viresh Kumar пишет:
> On 17-12-20, 21:06, Dmitry Osipenko wrote:
>> Add a ceil version of the dev_pm_opp_find_level(). It's handy to have if
>> levels don't start from 0 in OPP table and zero usually means a minimal
>> level.
>>
>> Signe
22.12.2020 11:55, Viresh Kumar пишет:
> On 17-12-20, 21:06, Dmitry Osipenko wrote:
>> Add resource-managed versions of OPP API functions. This removes a need
>> from drivers to store and manage OPP table pointers.
>>
>> Signed-off-by: Dmitry Osipenko
>> ---
22.12.2020 12:15, Viresh Kumar пишет:
> On 18-12-20, 16:51, Dmitry Osipenko wrote:
>> Alright, although I haven't pretended that v2 patches should be merged
>> right away since they are fundamentally different from v1, and thus, all
>> patches need to be reviewed first.
19.12.2020 14:02, Krzysztof Kozlowski пишет:
> On Thu, Dec 17, 2020 at 09:06:31PM +0300, Dmitry Osipenko wrote:
>> Use common devm_tegra_core_dev_init_opp_table() helper for the OPP table
>> initialization.
>>
>> Signed-off-by: Dmitry Osipenko
>> ---
>>
19.12.2020 13:57, Krzysztof Kozlowski пишет:
> On Thu, Dec 17, 2020 at 09:05:57PM +0300, Dmitry Osipenko wrote:
>> All NVIDIA Tegra SoCs have a core power domain where majority of hardware
>> blocks reside. Add binding for the core power domain.
>>
>> Sig
18.12.2020 10:14, Viresh Kumar пишет:
> On 17-12-20, 21:05, Dmitry Osipenko wrote:
>> Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs, which reduces
>> power consumption and heating of the Tegra chips. Tegra SoC has multiple
>> hardware units which belong to a cor
18.12.2020 00:19, Daniel Lezcano пишет:
> On 17/12/2020 21:28, Dmitry Osipenko wrote:
>> 17.12.2020 22:36, Daniel Lezcano пишет:
>>>>>> +
17.12.2020 21:45, Dmitry Osipenko пишет:
> 17.12.2020 21:21, Mikko Perttunen пишет:
>> On 12/17/20 8:06 PM, Dmitry Osipenko wrote:
>>> Add suspend/resume and generic power domain support to the Host1x driver.
>>> This is required for enabling system-wide DVFS and s
17.12.2020 22:36, Daniel Lezcano пишет:
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&trip
17.12.2020 21:28, Daniel Lezcano пишет:
> On 17/12/2020 19:06, Dmitry Osipenko wrote:
>> Enable CPU voltage scaling and thermal throttling on Tegra20 Ventana board.
>>
>> Signed-off-by: Dmitry Osipenko
>> ---
>> arch/arm/boot/dts/tegra20-ventana.dts | 40 +
17.12.2020 21:21, Mikko Perttunen пишет:
> On 12/17/20 8:06 PM, Dmitry Osipenko wrote:
>> Add suspend/resume and generic power domain support to the Host1x driver.
>> This is required for enabling system-wide DVFS and supporting dynamic
>> power management using a
ential clocks which don't use RPM and may be needed
during early boot.
2. Register all clocks that use RPM (and not needed early) at a later
boot time, once driver core is available.
That's the reason why this patch reshuffles registration of a few clocks.
Signed-off-by
Enable CPU voltage scaling and thermal throttling on Tegra30 Cardhu board.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra30-cardhu.dtsi | 61 ++-
1 file changed, 60 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi
b/arch/arm
Allow lower core voltages on Ventana board.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-ventana.dts | 32 ---
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts
b/arch/arm/boot/dts/tegra20-ventana.dts
: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/staging/media/tegra-vde/vde.c | 63 ++-
1 file changed, 53 insertions(+), 10 deletions(-)
diff --git a/drivers/staging/media/tegra-vde/vde.c
b/drivers/staging/media/tegra-vde/vde.c
index 28845b5bafaf..5be26b9bd5d8
Add OPP and add PM support to the GR3D driver. This is required for
enabling system-wide DVFS and supporting dynamic power management using
a generic power domain.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/gr3d.c | 264
Use common devm_tegra_core_dev_init_opp_table() helper for the OPP table
initialization.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra30-emc.c | 57 +++---
1 file changed, 4 insertions(+), 53 deletions(-)
diff --git a/drivers/memory/tegra/tegra30-emc.c
Add suspend/resume and generic power domain support to the Host1x driver.
This is required for enabling system-wide DVFS and supporting dynamic
power management using a generic power domain.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/host1x
voltage is allowed to go lower.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/regulators-tegra20.c | 19 ++-
drivers/soc/tegra/regulators-tegra30.c | 18 +-
2 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/tegra/regulators-tegra20
Add common helper which initializes OPP table for Tegra SoC core devices.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/common.c | 137 +
include/soc/tegra/common.h | 35 ++
2 files changed, 172 insertions(+)
diff --git a/drivers/soc/tegra
The device-tree compatibles are swapped in the code, correct them.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/gr2d.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tegra/gr2d.c b/drivers
for the core power domain in order to manage the voltage state of
the domain. This allows us to support a system-wide DVFS on Tegra.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/Kconfig | 6 ++
drivers/soc/tegra/Makefile| 1 +
drivers/soc/tegra/core-power
Add OPP tables and power domains to the Tegra20 device-tree.
Signed-off-by: Dmitry Osipenko
---
.../boot/dts/tegra20-acer-a500-picasso.dts| 4 +
arch/arm/boot/dts/tegra20-colibri.dtsi| 6 +-
arch/arm/boot/dts/tegra20-harmony.dts | 6 +-
arch/arm/boot/dts/tegra20-paz00
Print OPP level in debug message of _opp_add_static_v2(). This helps to
chase GENPD bugs.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/of.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/opp/of.c b/drivers/opp/of.c
index 1f2038a4420b..56b153ea5c56 100644
The debug message always prints rate=0 instead of a proper value, fix it.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/of.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/opp/of.c b/drivers/opp/of.c
index 3b5a4c8bc62f..1f2038a4420b 100644
--- a/drivers/opp
Add OPP tables and power domains to Tegra30 device-tree.
Signed-off-by: Dmitry Osipenko
---
.../tegra30-asus-nexus7-grouper-common.dtsi |4 +
arch/arm/boot/dts/tegra30-beaver.dts |4 +
arch/arm/boot/dts/tegra30-cardhu.dtsi | 20 +-
arch/arm/boot/dts/tegra30
Add OPP and SoC core voltage scaling support to the display controller
driver. This is required for enabling system-wide DVFS on pre-Tegra186
SoCs.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/dc.c | 66
Enable CPU voltage scaling and thermal throttling on Tegra20 Ventana board.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-ventana.dts | 40 ++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts
b/arch/arm
which should be use to the same clock rate, meanwhile voltage
scaling is done using a power domain. In this case OPP table doesn't have
a regulator, causing a NULL dereference in _set_opp_custom().
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 16
1 file changed, 12
Host1x channel should be idling before hardware is turned off, hence
stop the channel in the suspend callback.
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/vic.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra
Add resource-managed versions of OPP API functions. This removes a need
from drivers to store and manage OPP table pointers.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 173 +
drivers/opp/of.c | 25 ++
include/linux/pm_opp.h
Allow lower core voltages on Acer A500.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
Use common devm_tegra_core_dev_init_opp_table() helper for the OPP table
initialization.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra20-emc.c | 57 +++---
1 file changed, 4 insertions(+), 53 deletions(-)
diff --git a/drivers/memory/tegra/tegra20-emc.c
Add OPP and PM support to the GR2D driver. This is required for enabling
system-wide DVFS and supporting dynamic power management using a generic
power domain.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/gr2d.c | 73
: Dmitry Osipenko
---
drivers/gpu/host1x/channel.c | 8
include/linux/host1x.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/host1x/channel.c b/drivers/gpu/host1x/channel.c
index 4cd212bb570d..2a9a3a8d5931 100644
--- a/drivers/gpu/host1x/channel.c
+++ b/drivers
erformance change is applied to PMC domain.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index 4f96dc7745c4..1a659d1c06d7 100644
--- a/drivers/soc/tegra/pmc.c
+++
ns to
pass performance state to the parent domain if child's domain doesn't have
OPP table.
The dev_pm_opp_xlate_performance_state() gets src_table=NULL if a child
power domain doesn't have OPP table and in this case we should pass the
performance state to the parent domain.
Signe
-tree.
Fixes: 783807436f36 ("soc/tegra: regulators: Add regulators coupler for
Tegra30")
Cc: sta...@vger.kernel.org
Tested-by: Peter Geis
Reported-by: Peter Geis
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/regulators-tegra30.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
Add new Kconfig SOC_TEGRA_COMMON option which selects configuration
options that are common for all Tegra SoCs. Select PM_OPP by default
since from now on OPPs will be used by Tegra drivers which present on
all SoC generations, like display controller driver for example.
Signed-off-by: Dmitry
Print out domain name when reset fails to acquire for debugging purposes
and to make formatting of GENPD errors consistent in the driver.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/tegra/pmc.c b
Switch all clocks of a power domain to a safe rate which is suitable
for all possible voltages in order to ensure that hardware constraints
aren't violated when power domain state toggles.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c
Make set_performance_state() callback optional in order to remove the
need from power domain drivers to implement a dummy callback. If callback
isn't implemented by a GENPD driver, then the performance state is passed
to the parent domain.
Signed-off-by: Dmitry Osipenko
---
drivers/base/
The tegra_powergate_power_up() has a typo in the error code path where it
will try to disable clocks twice, fix it. In practice that error never
happens, so this is a minor correction.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
ower
gates are usually ungated after bootloader by default.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index fd2ba3c59178..985373ce52b1 100644
--- a/drivers/soc/tegra/p
Add a ceil version of the dev_pm_opp_find_level(). It's handy to have if
levels don't start from 0 in OPP table and zero usually means a minimal
level.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 49 ++
include/linux/pm_
Document "clocks" sub-node which describes Tegra SoC clocks that require
a higher voltage of the core power domain in order to operate properly on
a higher rates.
Signed-off-by: Dmitry Osipenko
---
.../bindings/clock/nvidia,tegra20-car.txt | 26 +++
.../bindings/cl
Add "performance" column to debug summary which shows performance state
of all power domains and theirs devices.
Signed-off-by: Dmitry Osipenko
---
drivers/base/power/domain.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/base/powe
Fix adding OPP entries in a wrong (opposite) order if OPP rate is
unavailable. The OPP comparison is erroneously skipped if OPP rate is
missing, thus OPPs are left unsorted.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 23 ---
drivers/opp/opp.h | 2 +-
2 files
Make regulator_sync_voltage() to re-balance voltage state of a coupled
regulators instead of changing the voltage directly.
Signed-off-by: Dmitry Osipenko
---
drivers/regulator/core.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
A required OPP may not be available, and thus, all OPPs which are using
this required OPP should be unavailable too.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/opp/core.c b/drivers/opp/core.c
Extend OPP API with dev_pm_opp_sync_regulators() function, which syncs
voltage state of regulators.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 42 ++
include/linux/pm_opp.h | 11 +++
2 files changed, 53 insertions(+)
diff --git a
Document new DVFS OPP table and power domain properties of the Host1x bus
and devices sitting on the bus.
Signed-off-by: Dmitry Osipenko
---
.../display/tegra/nvidia,tegra20-host1x.txt | 49 +++
1 file changed, 49 insertions(+)
diff --git
a/Documentation/devicetree/bindings
Add dev_pm_opp_set_voltage() which allows OPP table users to set voltage
in accordance to a given OPP. In particular this is needed for driving
voltage of a generic power domain which uses OPPs and doesn't have a
clock.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c
Add dev_pm_opp_get_required_pstate() which allows OPP users to retrieve
required performance state of a given OPP.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 22 ++
include/linux/pm_opp.h | 10 ++
2 files changed, 32 insertions(+)
diff --git a
All NVIDIA Tegra SoCs have a core power domain where majority of hardware
blocks reside. Add binding for the core power domain.
Signed-off-by: Dmitry Osipenko
---
.../arm/tegra/nvidia,tegra20-core-domain.yaml | 48 +++
1 file changed, 48 insertions(+)
create mode 100644
ulator yet, and thus, it's okay to change it.
Signed-off-by: Dmitry Osipenko
---
.../bindings/memory-controllers/nvidia,tegra124-emc.yaml| 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml
Document new DVFS OPP table and power domain properties of the video
decoder engine.
Signed-off-by: Dmitry Osipenko
---
.../devicetree/bindings/media/nvidia,tegra-vde.txt | 12
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/nvidia,tegra
ulator yet, and thus, it's okay to change it.
Signed-off-by: Dmitry Osipenko
---
.../bindings/memory-controllers/nvidia,tegra30-emc.yaml | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml
ions, as it was
discussed previously in the comments to v1.
- Added new APIs, features and fixed various bugs related to voltage
scaling and power management done via GENPD API.
Dmitry Osipenko (48):
dt-bindings: memory: tegra20: emc: Replace core regulator with power
domai
ulator yet, and thus, it's okay to change it.
Signed-off-by: Dmitry Osipenko
---
.../bindings/memory-controllers/nvidia,tegra20-emc.txt| 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.txt
01.12.2020 17:34, Mark Brown пишет:
> On Tue, Dec 01, 2020 at 05:17:20PM +0300, Dmitry Osipenko wrote:
>> 01.12.2020 16:57, Mark Brown пишет:
>
>>> [1/1] regulator: Allow skipping disabled regulators in
>>> regulator_check_consumers()
>>> (no comm
01.12.2020 16:57, Mark Brown пишет:
> On Thu, 5 Nov 2020 02:43:57 +0300, Dmitry Osipenko wrote:
>> Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs, which reduces
>> power consumption and heating of the Tegra chips. Tegra SoC has multiple
>> hardware units which b
23.11.2020 06:07, Ezequiel Garcia пишет:
> On Sat, 21 Nov 2020 at 23:01, Dmitry Osipenko wrote:
>>
>> 22.11.2020 04:02, Ezequiel Garcia пишет:
>>> Hi Dmitry,
>>>
>> ...
>>>> +++ b/drivers/staging/media/tegra-vde/TODO
>>>> @@ -0,0 +1,4
22.11.2020 04:02, Ezequiel Garcia пишет:
> Hi Dmitry,
>
...
>> +++ b/drivers/staging/media/tegra-vde/TODO
>> @@ -0,0 +1,4 @@
>> +TODO:
>> + - Implement V4L2 API once it gains support for stateless decoders.
>> +
>> +Contact: Dmitry Osipenko
>
&
16.11.2020 16:33, Mark Brown пишет:
> On Sun, Nov 15, 2020 at 08:42:10PM +0300, Dmitry Osipenko wrote:
>> 13.11.2020 20:28, Mark Brown пишет:
>
>>>> What should we do?
>
>>> As I keep saying the consumer driver should be enumerating the voltages
>>>
13.11.2020 20:28, Mark Brown пишет:
> On Fri, Nov 13, 2020 at 08:13:49PM +0300, Dmitry Osipenko wrote:
>> 13.11.2020 19:15, Mark Brown пишет:
>
>>> My point here is that the driver shouldn't be checking for a dummy
>>> regulator, the driver should be checking th
13.11.2020 19:35, Thierry Reding пишет:
> On Fri, Nov 13, 2020 at 01:14:45AM +0300, Dmitry Osipenko wrote:
>> 12.11.2020 23:43, Thierry Reding пишет:
>>>> The difference in comparison to using voltage regulator directly is
>>>> minimal, basically the core-suppl
13.11.2020 19:15, Mark Brown пишет:
> On Fri, Nov 13, 2020 at 06:55:27PM +0300, Dmitry Osipenko wrote:
>> 13.11.2020 17:29, Mark Brown пишет:
>
>>> It's not clear if it matters - it's more a policy decision on the part
>>> of the driver about what it thi
13.11.2020 17:45, Ulf Hansson пишет:
> On Thu, 12 Nov 2020 at 23:14, Dmitry Osipenko wrote:
>>
>> 12.11.2020 23:43, Thierry Reding пишет:
>>>> The difference in comparison to using voltage regulator directly is
>>>> minimal, basically the core-supply phan
13.11.2020 17:29, Mark Brown пишет:
> On Fri, Nov 13, 2020 at 01:37:01AM +0300, Dmitry Osipenko wrote:
>> 12.11.2020 23:01, Mark Brown пишет:
>>>> But it's not allowed to change voltage of a dummy regulator, is it
>>>> intentional?
>
>>> Of cour
12.11.2020 23:01, Mark Brown пишет:
>> But it's not allowed to change voltage of a dummy regulator, is it
>> intentional?
> Of course not, we can't know if the requested new voltage is valid - the
> driver would have to have explict support for handling situations where
> it's not possible to chang
12.11.2020 23:43, Thierry Reding пишет:
>> The difference in comparison to using voltage regulator directly is
>> minimal, basically the core-supply phandle is replaced is replaced with
>> a power-domain phandle in a device tree.
> These new power-domain handles would have to be added to devices th
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