[PATCH v13 4/4] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4d68184d3f76..02986055fdbc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11484,6 +11484,12 @@ L

[PATCH v13 3/4] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

. Acked-by: Greg Kroah-Hartman Acked-by: Thomas Bogendoerfer Signed-off-by: Sergio Paracuellos --- arch/mips/ralink/mt7621.c | 6 +++--- drivers/staging/mt7621-dts/mt7621.dtsi | 12 ++-- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/mips/ralink/mt7621

[PATCH v13 2/4] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v13 1/4] clk: ralink: add clock driver for mt7621 SoC

t;uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m&

[PATCH v13 0/4] MIPS: ralink: add CPU clock detection and clock driver for MT7621

tion 'clock-output-names'. Changes in v2: - Remove the following patches: * dt: bindings: add mt7621-pll device tree binding documentation. * MIPS: ralink: add clock device providing cpu/ahb/apb clock for mt7621. - Move all relevant clock code to 'drivers/clk/ralink/clk-mt76

[PATCH v12 4/4] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 809a68af5efd..ecad5d972122 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11288,6 +11288,12 @@ L

[PATCH v12 1/4] clk: ralink: add clock driver for mt7621 SoC

t;uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m&

[PATCH v12 2/4] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v12 0/4] MIPS: ralink: add CPU clock detection and clock driver for MT7621

ecause of ignoring return values of 'of_clk_hw_register' in functions 'mt7621_register_top_clocks' and 'mt7621_gate_ops_init'. - Fix dts file and binding documentation 'clock-output-names'. Changes in v2: - Remove the following patches: * dt:

[PATCH v12 3/4] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

. Acked-by: Greg Kroah-Hartman Acked-by: Thomas Bogendoerfer Signed-off-by: Sergio Paracuellos --- arch/mips/ralink/mt7621.c | 6 +++--- drivers/staging/mt7621-dts/mt7621.dtsi | 12 ++-- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/mips/ralink/mt7621

Re: [PATCH v11 3/6] clk: ralink: add clock driver for mt7621 SoC

Hi, On Fri, Apr 9, 2021 at 8:14 PM Stephen Boyd wrote: > > Quoting Sergio Paracuellos (2021-03-08 21:22:23) > > diff --git a/drivers/clk/ralink/Kconfig b/drivers/clk/ralink/Kconfig > > new file mode 100644 > > index ..3e3f5cb9ad88 > > --- /dev/nul

Re: [PATCH v11 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

Hi Stephen, On Tue, Mar 9, 2021 at 6:22 AM Sergio Paracuellos wrote: > > This patchset ports CPU clock detection for MT7621 from OpenWrt > and adds a complete clock plan for the mt7621 SOC. > > The documentation for this SOC only talks about two registers > regar

[PATCH v11 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 809a68af5efd..ecad5d972122 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11288,6 +11288,12 @@ L

[PATCH v11 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

ted code to properly match new strings. Even there are used in the device tree there are some strings that are not referred anywhere but have been also updated with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand', 'mtk,mt7621-mc', and 'mtk,mt7621-cpc&#

[PATCH v11 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v11 3/6] clk: ralink: add clock driver for mt7621 SoC

t;uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m&

[PATCH v11 2/6] dt: bindings: add mt7621-sysc device tree binding documentation

Adds device tree binding documentation for clocks in the MT7621 SOC. Reviewed-by: Rob Herring Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-sysc.yaml | 68 +++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings

[PATCH v11 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h di

[PATCH v11 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

ns 'mt7621_register_top_clocks' and 'mt7621_gate_ops_init'. - Fix dts file and binding documentation 'clock-output-names'. Changes in v2: - Remove the following patches: * dt: bindings: add mt7621-pll device tree binding documentation. * MIPS: ralink: add clock device providin

[PATCH v10 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 809a68af5efd..be5ada6b4309 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11288,6 +11288,12 @@ L

[PATCH v10 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

ted code to properly match new strings. Even there are used in the device tree there are some strings that are not referred anywhere but have been also updated with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand', 'mtk,mt7621-mc', and 'mtk,mt7621-cpc&#

[PATCH v10 3/6] clk: ralink: add clock driver for mt7621 SoC

t;uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m&

[PATCH v10 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v10 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h di

[PATCH v10 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

the following patches: * dt: bindings: add mt7621-pll device tree binding documentation. * MIPS: ralink: add clock device providing cpu/ahb/apb clock for mt7621. - Move all relevant clock code to 'drivers/clk/ralink/clk-mt7621.c' and unify there previous 'mt7621-pll' and &#

[PATCH v10 2/6] dt: bindings: add mt7621-sysc device tree binding documentation

Adds device tree binding documentation for clocks in the MT7621 SOC. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-sysc.yaml | 68 +++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621

Re: [PATCH v9 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Hi, On Sat, Mar 6, 2021 at 10:54 AM Sergio Paracuellos wrote: > > Hi again, > > On Sat, Mar 6, 2021 at 8:12 AM Sergio Paracuellos > wrote: > > > > Hi Rob, > > > > On Fri, Mar 5, 2021 at 11:47 PM Rob Herring wrote: > > [snip] > > > >

Re: [PATCH v9 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Hi again, On Sat, Mar 6, 2021 at 8:12 AM Sergio Paracuellos wrote: > > Hi Rob, > > On Fri, Mar 5, 2021 at 11:47 PM Rob Herring wrote: > [snip] > > > + > > > + ralink,sysctl: > > > +$ref: /schemas/types.yaml#/definitions/phandle > > > +

Re: [PATCH v9 2/6] dt: bindings: add mt7621-clk device tree binding documentation

ious version" on this patch, please guide me in the correct thing to do. Stephen, Rob, I will be really happy with your help :) Best regards, Sergio Paracuellos > > > + > > + clock-output-names: > > +maxItems: 8 > > + > > +required: &

[PATCH] phy: ralink: phy-mt7621-pci: fix XTAL bitmask

When this was rewriten to get mainlined and start to use 'linux/bitfield.h' headers, XTAL_MASK was wrong. It must mask three bits but only two were used. Hence properly fix it to make things work. Fixes: d87da32372a0 ("phy: ralink: Add PHY driver for MT7621 PCIe PHY") S

[PATCH v9 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 809a68af5efd..be5ada6b4309 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11288,6 +11288,12 @@ L

[PATCH v9 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

ted code to properly match new strings. Even there are used in the device tree there are some strings that are not referred anywhere but have been also updated with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand', 'mtk,mt7621-mc', and 'mtk,mt7621-cpc&#

[PATCH v9 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v9 3/6] clk: ralink: add clock driver for mt7621 SoC

t;uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m&

[PATCH v9 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h di

[PATCH v9 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Adds device tree binding documentation for clocks in the MT7621 SOC. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-clk.yaml | 66 +++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621

[PATCH v9 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

mt7621_gate_ops_init'. - Fix dts file and binding documentation 'clock-output-names'. Changes in v2: - Remove the following patches: * dt: bindings: add mt7621-pll device tree binding documentation. * MIPS: ralink: add clock device providing cpu/ahb/apb clock for mt7621. - Move all relevant clock code to &

[PATCH v8 3/6] clk: ralink: add clock driver for mt7621 SoC

t;uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m&

[PATCH v8 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

'of_clk_hw_register' in functions 'mt7621_register_top_clocks' and 'mt7621_gate_ops_init'. - Fix dts file and binding documentation 'clock-output-names'. Changes in v2: - Remove the following patches: * dt: bindings: add mt7621-pll device tree b

[PATCH v8 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

ted code to properly match new strings. Even there are used in the device tree there are some strings that are not referred anywhere but have been also updated with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand', 'mtk,mt7621-mc', and 'mtk,mt7621-cpc&#

[PATCH v8 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 809a68af5efd..be5ada6b4309 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11288,6 +11288,12 @@ L

[PATCH v8 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v8 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Adds device tree binding documentation for clocks in the MT7621 SOC. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-clk.yaml | 66 +++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621

[PATCH v8 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h di

[PATCH v7 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 809a68af5efd..be5ada6b4309 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11288,6 +11288,12 @@ L

[PATCH v7 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

ted code to properly match new strings. Even there are used in the device tree there are some strings that are not referred anywhere but have been also updated with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand', 'mtk,mt7621-mc', and 'mtk,mt7621-cpc&#

[PATCH v7 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Adds device tree binding documentation for clocks in the MT7621 SOC. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-clk.yaml | 66 +++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621

[PATCH v7 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v7 3/6] clk: ralink: add clock driver for mt7621 SoC

t;uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m&

[PATCH v7 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

'. - Fix dts file and binding documentation 'clock-output-names'. Changes in v2: - Remove the following patches: * dt: bindings: add mt7621-pll device tree binding documentation. * MIPS: ralink: add clock device providing cpu/ahb/apb clock for mt7621. - Move all relevant clock

[PATCH v7 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h di

Re: [PATCH v2] Staging: mt7621-pci: fixed a blank line coding style issue

(-) Reviewed-by: Sergio Paracuellos Best regards, Sergio Paracuellos ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel

Re: [PATCH] Staging: mt7621-pci: pci-mt7621: fixed a blank line coding style issue

t; } > } > -- > 2.17.1 > Please, also change commit short message to: staging: mt7621-pci: fixed a blank line coding style issue With that changes: Reviewed-by: Sergio Paracuellos Best regards, Sergio Paracuellos ___ devel mailing

[PATCH v6 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

ted code to properly match new strings. Even there are used in the device tree there are some strings that are not referred anywhere but have been also updated with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand', 'mtk,mt7621-mc', and 'mtk,mt7621-cpc&#

[PATCH v6 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Acked-by: Greg Kroah-Hartman Signed-off-by: Sergio Paracuellos

[PATCH v6 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 809a68af5efd..be5ada6b4309 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11288,6 +11288,12 @@ L

[PATCH v6 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

functions 'mt7621_register_top_clocks' and 'mt7621_gate_ops_init'. - Fix dts file and binding documentation 'clock-output-names'. Changes in v2: - Remove the following patches: * dt: bindings: add mt7621-pll device tree binding documentation. * MIPS: ralin

[PATCH v6 3/6] clk: ralink: add clock driver for mt7621 SoC

t;uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m&

[PATCH v6 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Adds device tree binding documentation for clocks in the MT7621 SOC. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-clk.yaml | 66 +++ 1 file changed, 66 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621

[PATCH v6 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h di

[RESEND PATCH v5 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h di

[RESEND PATCH v5 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

on 'clock-output-names'. Changes in v2: - Remove the following patches: * dt: bindings: add mt7621-pll device tree binding documentation. * MIPS: ralink: add clock device providing cpu/ahb/apb clock for mt7621. - Move all relevant clock code to 'drivers/clk/ralink/clk-mt7621.c&#

[RESEND PATCH v5 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f5eafee83bc6..f0c51d9760ec 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11247,6 +11247,12 @@ L

[RESEND PATCH v5 3/6] clk: ralink: add clock driver for mt7621 SoC

t;uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m&q

[RESEND PATCH v5 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

ted code to properly match new strings. Even there are used in the device tree there are some strings that are not referred anywhere but have been also updated with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand', 'mtk,mt7621-mc', and 'mtk,mt7621-cpc

[RESEND PATCH v5 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-dts

[RESEND PATCH v5 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Adds device tree binding documentation for clocks in the MT7621 SOC. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-clk.yaml | 52 +++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621

Re: [PATCH v5 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

Hi all, On Sun, Dec 20, 2020 at 10:37 AM Sergio Paracuellos wrote: > > This patchset ports CPU clock detection for MT7621 from OpenWrt > and adds a complete clock plan for the mt7621 SOC. > > The documentation for this SOC only talks about two registers > regar

Re: [PATCH] staging: mt7621-dts: remove obsolete switch node

- > 1 file changed, 7 deletions(-) Reviewed-by: Sergio Paracuellos ___ devel mailing list de...@linuxdriverproject.org http://driverdev.linuxdriverproject.org/mailman/listinfo/driverdev-devel

[PATCH] staging: mt7621-dts: match pinctrl nodes with its binding documentation

According to the binding documentation pinctrl related nodes must use '-pins$' and ''^(.*-)?pinmux$'' as names. Change all to properly match them. Also default state is for consumer nodes and shall be removed from here. Signed-off-by: Sergio Paracuellos --- dri

Re: [PATCH 0/8] pinctrl: ralink: rt2880: Some minimal clean ups

Hi, On Mon, Jan 4, 2021 at 3:39 PM Linus Walleij wrote: > > On Sun, Dec 13, 2020 at 5:17 PM Sergio Paracuellos > wrote: > > > After this driver was moved from staging into pinctrl subsytems > > some reviews for bindigns and driver itself comes from Ron Herring > >

Re: [PATCH v5 2/6] dt: bindings: add mt7621-clk device tree binding documentation

On Fri, Jan 1, 2021 at 12:51 AM Sergio Paracuellos wrote: > > Hi Rob, > > Thanks for the review. Hi again, > > On Thu, Dec 31, 2020 at 11:38 PM Rob Herring wrote: > > > > On Sun, Dec 20, 2020 at 10:37:20AM +0100, Sergio Paracuellos wrote: > > > Adds devic

Re: [PATCH v5 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Hi Rob, Thanks for the review. On Thu, Dec 31, 2020 at 11:38 PM Rob Herring wrote: > > On Sun, Dec 20, 2020 at 10:37:20AM +0100, Sergio Paracuellos wrote: > > Adds device tree binding documentation for clocks in the > > MT7621 SOC. > > > > Sig

[PATCH v5 6/6] MAINTAINERS: add MT7621 CLOCK maintainer

Adding myself as maintainer for mt7621 clock driver. Signed-off-by: Sergio Paracuellos --- MAINTAINERS | 6 ++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index f5eafee83bc6..f0c51d9760ec 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11247,6 +11247,12 @@ L

[PATCH v5 5/6] staging: mt7621-dts: use valid vendor 'mediatek' instead of invalid 'mtk'

ted code to properly match new strings. Even there are used in the device tree there are some strings that are not referred anywhere but have been also updated with new vendor name. These are 'mtk,mt7621-wdt', 'mtk,mt7621-nand', 'mtk,mt7621-mc', and 'mtk,mt7621-cpc

[PATCH v5 1/6] dt-bindings: clock: add dt binding header for mt7621 clocks

Adds dt binding header for 'mediatek,mt7621-clk' clocks. Acked-by: Rob Herring Signed-off-by: Sergio Paracuellos --- include/dt-bindings/clock/mt7621-clk.h | 41 ++ 1 file changed, 41 insertions(+) create mode 100644 include/dt-bindings/clock/mt7621-clk.h di

[PATCH v5 4/6] staging: mt7621-dts: make use of new 'mt7621-clk'

Clocks for SoC mt7621 have been properly integrated so there is no need to declare fixed clocks at all in the device tree. Remove all of them, add new device tree nodes for mt7621-clk and update the rest of the nodes to use them. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-dts

[PATCH v5 3/6] clk: ralink: add clock driver for mt7621 SoC

t;uart1": "50m" * "uart2": "50m" * "uart3": "50m" * "eth": "50m" * "pcie0": "125m" * "pcie1": "125m" * "pcie2": "125m" * "crypto": "250m&q

[PATCH v5 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Adds device tree binding documentation for clocks in the MT7621 SOC. Signed-off-by: Sergio Paracuellos --- .../bindings/clock/mediatek,mt7621-clk.yaml | 52 +++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621

[PATCH v5 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

t'. - Fix dts file and binding documentation 'clock-output-names'. Changes in v2: - Remove the following patches: * dt: bindings: add mt7621-pll device tree binding documentation. * MIPS: ralink: add clock device providing cpu/ahb/apb clock for mt7621. - Move all relevant clock

Re: [PATCH v4 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Hi Rob, On Thu, Dec 17, 2020 at 4:05 PM Rob Herring wrote: > > On Thu, Dec 17, 2020 at 2:58 AM Stephen Boyd wrote: > > > > Quoting Sergio Paracuellos (2020-11-22 01:55:52) > > > Adds device tree binding documentation for clocks in the > > > MT7621 SO

Re: [PATCH v4 2/6] dt: bindings: add mt7621-clk device tree binding documentation

Hi Stephen, Thanks for the review! On Thu, Dec 17, 2020 at 9:58 AM Stephen Boyd wrote: > > Quoting Sergio Paracuellos (2020-11-22 01:55:52) > > Adds device tree binding documentation for clocks in the > > MT7621 SOC. > > > > Signed-off-by: Sergio Paracuellos &

Re: [PATCH v4 3/6] clk: ralink: add clock driver for mt7621 SoC

Hi Stephen, Thanks for the review. On Thu, Dec 17, 2020 at 10:09 AM Stephen Boyd wrote: > > Quoting Sergio Paracuellos (2020-11-22 01:55:53) > > The documentation for this SOC only talks about two > > registers regarding to the clocks: > > * SYSC_REG_CPLL_CLKCFG0 - p

Re: [PATCH 0/8] pinctrl: ralink: rt2880: Some minimal clean ups

On Mon, Dec 14, 2020 at 10:02 AM Linus Walleij wrote: > > On Sun, Dec 13, 2020 at 5:17 PM Sergio Paracuellos > wrote: > > > After this driver was moved from staging into pinctrl subsytems > > some reviews for bindigns and driver itself comes from Ron Herring > > and

[PATCH 8/8] staging: mt7621-dts: properly name pinctrl related nodes

According to the binding documentation pinctrl related nodes must use '-pins$' and ''^(.*-)?pinmux$'' as names. Change all of them to properly match them. Signed-off-by: Sergio Paracuellos --- drivers/staging/mt7621-dts/mt7621.dtsi | 46 +-

[PATCH 7/8] pinctrl: ralink: rt2880: use 'PTR_ERR_OR_ZERO'

Avoid some boilerplate code using 'PTR_ERR_OR_ZERO' in probe function. Signed-off-by: Sergio Paracuellos --- drivers/pinctrl/ralink/pinctrl-rt2880.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/pinctrl/ralink/pinctrl-rt2880.c b/drivers/pinctrl/rali

[PATCH 5/8] pinctrl: ralink: rt2880: delete not needed error message

When '-ENOMEM' is returned there is not need at all to add custom error messages. Hence delete it. Reported-by: Dan Carpenter Signed-off-by: Sergio Paracuellos --- drivers/pinctrl/ralink/pinctrl-rt2880.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drive

[PATCH 6/8] pinctrl: ralink: rt2880: preserve error codes

Some paths in probe function are returning '-EINVAL' instead of preserve original code from called functions. Change them to preserve all of them. Reported-by: Dan Carpenter Signed-off-by: Sergio Paracuellos --- drivers/pinctrl/ralink/pinctrl-rt2880.c | 12 1 file

[PATCH 3/8] pinctrl: ralink: rt2880: return proper error code

Check for NULL shall return '-ENOMEM' instead of '-1'. Reported-by: Dan Carpenter Signed-off-by: Sergio Paracuellos --- drivers/pinctrl/ralink/pinctrl-rt2880.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/ralink/pinctrl-rt2880.c b/dr

[PATCH 4/8] pinctrl: ralink: rt2880: add missing NULL check

Memory is being requested to the kernel but there is a missing check for NULL. Hence, add it. Reported-by: Dan Carpenter Signed-off-by: Sergio Paracuellos --- drivers/pinctrl/ralink/pinctrl-rt2880.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pinctrl/ralink/pinctrl-rt2880.c

[PATCH 2/8] pinctrl: ralink: rt2880: avoid double pointer to simplify code

Double pointer is being used and assigned in a bit dirty way to assign functions in pinctrl. Instead of doing this just avoid it and use directly 'p->func' instead. Reported-by: Dan Carpenter Signed-off-by: Sergio Paracuellos --- drivers/pinctrl/ralink/pinctrl-

[PATCH 1/8] dt-bindings: pinctrl: rt2880: properly redo bindings

ncluded inside a new '^(.*-)?pinmux$' node. - compatible string is not an 'enum' but a 'const'. - 'pinctrl-0' and 'pinctrl-names' removed since they are used in consumer nodes. Signed-off-by: Sergio Paracuellos --- .../pinctrl/ralink,rt2880-pinmux

[PATCH 0/8] pinctrl: ralink: rt2880: Some minimal clean ups

After this driver was moved from staging into pinctrl subsytems some reviews for bindigns and driver itself comes from Ron Herring and Dan Carpenter. Get rid of all the comments to properly be in a good shape before merge window. Best regards, Sergio Paracuellos Sergio Paracuellos (8): dt

Re: [PATCH v2 1/2] dt-bindings: pinctrl: rt2880: add binding document

Hi Rob, On Thu, Dec 10, 2020 at 2:47 PM Rob Herring wrote: > > On Tue, Dec 08, 2020 at 08:55:22AM +0100, Sergio Paracuellos wrote: > > The commit adds rt2880 compatible node in binding document. > > > > Signed-off-by: Sergio Paracuellos > > --- > > .

Re: [PATCH v4 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

Hi all, On Sun, Nov 22, 2020 at 10:55 AM Sergio Paracuellos wrote: > > This patchset ports CPU clock detection for MT7621 from OpenWrt > and adds a complete clock plan for the mt7621 SOC. > > The documentation for this SOC only talks about two registers > regar

Re: [PATCH 2/3] pinctrl: ralink: add a pinctrl driver for the rt2880 family

Hi Dan, Thanks for the review. On Tue, Dec 8, 2020 at 11:17 AM Dan Carpenter wrote: > > On Mon, Dec 07, 2020 at 08:21:03PM +0100, Sergio Paracuellos wrote: > > +static struct pinctrl_desc rt2880_pctrl_desc = { > > + .owner = THIS_MODULE, > > + .name

Re: [PATCH v2 2/2] pinctrl: ralink: add a pinctrl driver for the rt2880 family

On Tue, Dec 8, 2020 at 10:03 AM Greg KH wrote: > > On Tue, Dec 08, 2020 at 09:21:31AM +0100, Linus Walleij wrote: > > On Tue, Dec 8, 2020 at 8:55 AM Sergio Paracuellos > > wrote: > > > > > These Socs have 1-3 banks of 8-32 gpios. Rather then setting th

[PATCH v2 2/2] pinctrl: ralink: add a pinctrl driver for the rt2880 family

These Socs have 1-3 banks of 8-32 gpios. Rather then setting the muxing of each pin individually, these socs have mux groups that when set will effect 1-N pins. Pin groups have a 2, 4 or 8 different muxes. Acked-by: Linus Walleij Signed-off-by: Sergio Paracuellos --- drivers/pinctrl/Kconfig

[PATCH v2 1/2] dt-bindings: pinctrl: rt2880: add binding document

The commit adds rt2880 compatible node in binding document. Signed-off-by: Sergio Paracuellos --- .../pinctrl/ralink,rt2880-pinmux.yaml | 70 +++ 1 file changed, 70 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.yaml

[PATCH v2 0/2] pinctrl: ralink: pinctrl driver for the rt2880 family

ble to validate using 'dt_binding_check' with errors in all pinctrl nodes because are not of type 'object'. Best regards, Sergio Paracuellos [0]: http://driverdev.linuxdriverproject.org/pipermail/driverdev-devel/2020-December/149178.html [1]: http://driverdev.linuxdr

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