On Sat, Apr 10, 2021 at 5:02 AM Stephen Boyd wrote:
>
> Quoting Michal Simek (2021-04-08 03:40:29)
> >
> >
> > On 4/8/21 12:26 PM, Shubhrajyoti Datta wrote:
> > > On Sun, Mar 7, 2021 at 1:50 AM Rob Herring wrote:
> > >>
> > >> On Wed, F
On Sun, Mar 7, 2021 at 1:50 AM Rob Herring wrote:
>
> On Wed, Feb 24, 2021 at 06:40:40PM +0530, Shubhrajyoti Datta wrote:
> > Add the devicetree binding for the xilinx clocking wizard.
> >
> > Signed-off-by: Shubhrajyoti Datta
> > ---
> > v6:
> > F
On Mon, Mar 15, 2021 at 12:37 PM Zhengxun Li wrote:
>
> Hi Shubhrajyoti,
>
> My name is Zhengxun and I am the engineer from Macronix. We are
> using the platform PicoZed 7015/7030 SOM (System On Module),
> which is based on Xilinx Zynq®-7000 All Programmable (AP) SoC to
> verify our Flash driver.
Hi Zhengxun,
On Mon, Mar 15, 2021 at 12:55 PM Zhengxun Li wrote:
>
> Hi Shubhrajyoti,
>
> +static int clk_wzrd_dynamic_reconfig_f(struct clk_hw *hw, unsigned long rate,
> + unsigned long parent_rate)
> +{
> + int err;
> + u32 value, pre;
> + unsigned long rate_div, f, clockout0_div;
> +
Hi Zhengxun,
Thanks for the review.
On Mon, Mar 15, 2021 at 12:37 PM Zhengxun Li wrote:
>
> Hi Shubhrajyoti,
>
> My name is Zhengxun and I am the engineer from Macronix. We are
> using the platform PicoZed 7015/7030 SOM (System On Module),
> which is based on Xilinx Zynq®-7000 All Programmable
The patch adds support for dynamic reconfiguration of clock output rate.
Output clocks are registered as dividers and set rate callback function
is used for dynamic reconfiguration.
Signed-off-by: Shubhrajyoti Datta
Co-developed-by: Chirag Parekh
---
v6:
Remove the typecast.
use min for capping
The number of output clocks are configurable in the hardware.
Currently the driver registers the maximum number of outputs.
Fix the same by registering only the outputs that are there.
Signed-off-by: Shubhrajyoti Datta
---
v10:
generate the names runtime.
drivers/staging/clocking-wizard/clk
Update the fixed factor clock registration to register the divisors.
Signed-off-by: Shubhrajyoti Datta
---
drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock
Add the devicetree binding for the xilinx clocking wizard.
Signed-off-by: Shubhrajyoti Datta
---
v6:
Fix a yaml warning
v7:
Add vendor prefix speed-grade
v8:
Fix the warnings
v10:
Add nr-outputs
.../bindings/clock/xlnx,clocking-wizard.yaml | 72 ++
1 file
If there is only one output then allow changing of the parent rate.
Signed-off-by: Shubhrajyoti Datta
---
drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
b/drivers
Rename speed-grade to xlnx,speed-grade
Signed-off-by: Shubhrajyoti Datta
---
drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
b/drivers/staging/clocking-wizard/clk
Add clocking wizard driver to clk.
And delete the driver from the staging as it is in drivers/clk.
Signed-off-by: Shubhrajyoti Datta
---
drivers/clk/Kconfig| 9 +++
drivers/clk/Makefile | 1 +
.../clk-xlnx-clock-wizard.c
Currently the set rate granularity is to integral divisors.
Add support for the fractional divisors.
Only the first output0 is fractional in the hardware.
Signed-off-by: Shubhrajyoti Datta
---
v7:
Remove unnecessary comments
use mult_frac
use a common divisor function.
.../clocking-wizard/clk
the patches
Update the speed grade description.
[1] https://spinics.net/lists/linux-driver-devel/msg117326.html
Shubhrajyoti Datta (9):
staging: clocking-wizard: Fix kernel-doc warning
staging: clocking-wizard: Rename speed-grade to xlnx,speed-grade
staging: clocking-wizard: Update the fixed
Fix the clocking wizard main structure kernel documentation.
Signed-off-by: Shubhrajyoti Datta
---
v10:
Updated the description
drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/clocking-wizard/clk-xlnx
Update description for the clocking wizard structure
Signed-off-by: Shubhrajyoti Datta
---
drivers/clk/clk-xlnx-clock-wizard.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c
b/drivers/clk/clk-xlnx-clock-wizard.c
index 1bab68e..fb2d555
The patch adds support for dynamic reconfiguration of clock output rate.
Output clocks are registered as dividers and set rate callback function
is used for dynamic reconfiguration.
Based on the initial work from Chirag.
Signed-off-by: Chirag Parekh
Signed-off-by: Shubhrajyoti Datta
---
v6
Currently the set rate granularity is to integral divisors.
Add support for the fractional divisors.
Only the first output0 is fractional in the hardware.
Signed-off-by: Shubhrajyoti Datta
---
v7:
Remove unnecessary comments
use mult_frac
use a common divisor function.
drivers/clk/clk-xlnx
The number of output clocks are configurable in the hardware.
Currently the driver registers the maximum number of outputs.
Fix the same by registering only the outputs that are there.
Signed-off-by: Shubhrajyoti Datta
---
v4:
Assign output in this patch
drivers/clk/clk-xlnx-clock-wizard.c | 6
Update the fixed factor clock registration to register the divisors.
Signed-off-by: Shubhrajyoti Datta
---
drivers/clk/clk-xlnx-clock-wizard.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c
b/drivers/clk/clk-xlnx-clock
Add the devicetree binding for the xilinx clocking wizard.
Signed-off-by: Shubhrajyoti Datta
---
v6:
Fix a yaml warning
v7:
Add vendor prefix speed-grade
.../bindings/clock/xlnx,clocking-wizard.yaml | 65 ++
1 file changed, 65 insertions(+)
create mode 100644
Add clocking wizard driver to clk.
And delete the driver from the staging as it is in drivers/clk.
Signed-off-by: Shubhrajyoti Datta
---
v7:
Combined the patch for deletion and add of the driver
dropping the ack from Greg for the staging as it is a combined patch.
Add vendor prefix to speedgrade
Shubhrajyoti Datta (7):
dt-bindings: add documentation of xilinx clocking wizard
clk: clock-wizard: Add the clockwizard to clk directory
clk: clock-wizard: Fix kernel-doc warning
clk: clock-wizard: Add support for dynamic reconfiguration
clk: clock-wizard: Add support for fractional support
Hi Stephen,
Thanks for the review.
> -Original Message-
> From: Stephen Boyd
> Sent: Tuesday, September 22, 2020 2:52 AM
> To: Shubhrajyoti Datta ; linux-...@vger.kernel.org
> Cc: devicet...@vger.kernel.org; linux-ker...@vger.kernel.org;
> de...@driverdev.osuosl.org;
Hi ,
Thanks for the review.
> -Original Message-
> From: Stephen Boyd
> Sent: Tuesday, September 22, 2020 2:48 AM
> To: Shubhrajyoti Datta ; linux-...@vger.kernel.org
> Cc: devicet...@vger.kernel.org; linux-ker...@vger.kernel.org;
> de...@driverdev.osuosl.org; robh...
Update the fixed factor clock registration to register the divisors.
Signed-off-by: Shubhrajyoti Datta
---
drivers/clk/clk-xlnx-clock-wizard.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c
b/drivers/clk/clk-xlnx-clock
The patch adds support for dynamic reconfiguration of clock output rate.
Output clocks are registered as dividers and set rate callback function
is used for dynamic reconfiguration.
Based on the initial work from Chirag.
Signed-off-by: Chirag Parekh
Signed-off-by: Shubhrajyoti Datta
---
v6
Add the devicetree binding for the xilinx clocking wizard.
Signed-off-by: Shubhrajyoti Datta
---
v6:
Fix a yaml warning
.../bindings/clock/xlnx,clocking-wizard.yaml | 71 ++
1 file changed, 71 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock
The number of output clocks are configurable in the hardware.
Currently the driver registers the maximum number of outputs.
Fix the same by registering only the outputs that are there.
Signed-off-by: Shubhrajyoti Datta
---
v4:
Assign output in this patch
drivers/clk/clk-xlnx-clock-wizard.c | 6
Delete the driver from the staging as it is in drivers/clk.
Signed-off-by: Shubhrajyoti Datta
Acked-by: Greg Kroah-Hartman
---
drivers/staging/Kconfig| 2 -
drivers/staging/Makefile | 1 -
drivers/staging/clocking-wizard/Kconfig
Currently the set rate granularity is to integral divisors.
Add support for the fractional divisors.
Only the first output0 is fractional in the hardware.
Signed-off-by: Shubhrajyoti Datta
---
v6:
remove unnecessary typecast
remove unnecessary locks
use polled timeout
drivers/clk/clk-xlnx
Update description for the clocking wizard structure
Signed-off-by: Shubhrajyoti Datta
---
drivers/clk/clk-xlnx-clock-wizard.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c
b/drivers/clk/clk-xlnx-clock-wizard.c
index b31524a..d6577c8
staging as suggested
v4:
Reorder the patches.
Merge the CLK_IS_BASIC patch.
Add the yaml form of binding document
v5:
Fix a mismerge
v6:
Fix the yaml warning
use poll timedout
[1] https://spinics.net/lists/linux-driver-devel/msg117326.html
Shubhrajyoti Datta (8):
dt-bindings: add documentation
Add clocking wizard driver to clk.
Signed-off-by: Shubhrajyoti Datta
---
drivers/clk/Kconfig | 9 +
drivers/clk/Makefile| 1 +
drivers/clk/clk-xlnx-clock-wizard.c | 338
3 files changed, 348 insertions(+)
create mode
On Mon, Jan 6, 2020 at 1:30 AM Stephen Boyd wrote:
>
> Quoting shubhrajyoti.da...@gmail.com (2019-11-27 22:36:14)
> > From: Shubhrajyoti Datta
> >
> > Update the fixed factor clock registration to register the divisors.
> >
> > Signed-off-by: Shubhrajyoti Datt
On Thu, Nov 28, 2019 at 1:15 PM Dan Carpenter wrote:
>
> On Thu, Nov 28, 2019 at 12:06:15PM +0530, shubhrajyoti.da...@gmail.com wrote:
> > From: Shubhrajyoti Datta
> >
> > Incase there are more than one instance of the clocking wizard.
> > And if the output name gi
From: Shubhrajyoti Datta
Incase there are more than one instance of the clocking wizard.
And if the output name given is the same then the probe fails.
Fix the same by appending the device name to the output name to
make it unique.
Signed-off-by: Shubhrajyoti Datta
---
drivers/clk/clk-xlnx
From: Shubhrajyoti Datta
Delete the driver from the staging as it is in drivers/clk.
Signed-off-by: Shubhrajyoti Datta
---
drivers/staging/Kconfig| 2 -
drivers/staging/Makefile | 1 -
drivers/staging/clocking-wizard/Kconfig
From: Shubhrajyoti Datta
Update the fixed factor clock registration to register the divisors.
Signed-off-by: Shubhrajyoti Datta
---
drivers/clk/clk-xlnx-clock-wizard.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c
b
From: Shubhrajyoti Datta
Update description for the clocking wizard structure
Signed-off-by: Shubhrajyoti Datta
---
drivers/clk/clk-xlnx-clock-wizard.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-xlnx-clock-wizard.c
b/drivers/clk/clk-xlnx-clock
From: Shubhrajyoti Datta
In the thread [1] Greg suggested that we move the driver
to the clk from the staging.
Add patches to address the concerns regarding the fractional and
set rate support in the TODO.
The patch set does the following
- Trivial fixes for kernel doc.
- Move the driver
From: Shubhrajyoti Datta
The number of output clocks are configurable in the hardware.
Currently the driver registers the maximum number of outputs.
Fix the same by registering only the outputs that are there.
Signed-off-by: Shubhrajyoti Datta
---
drivers/clk/clk-xlnx-clock-wizard.c | 5
From: Shubhrajyoti Datta
After 90b6c5c73 (clk: Remove CLK_IS_BASIC clk flag)
The CLK_IS_BASIC is deleted. Adapt the driver for the same.
Signed-off-by: Shubhrajyoti Datta
---
drivers/clk/clk-xlnx-clock-wizard.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers
From: Shubhrajyoti Datta
Currently the set rate granularity is to integral divisors.
Add support for the fractional divisors.
Only the first output0 is fractional in the hardware.
Signed-off-by: Shubhrajyoti Datta
---
drivers/clk/clk-xlnx-clock-wizard.c | 192
From: Shubhrajyoti Datta
Add the devicetree binding for the xilinx clocking wizard.
Signed-off-by: Shubhrajyoti Datta
---
.../bindings/clock/xlnx,clocking-wizard.txt| 32 ++
1 file changed, 32 insertions(+)
create mode 100644
Documentation/devicetree/bindings
From: Shubhrajyoti Datta
Move the clocking wizard driver from staging to clk.
Signed-off-by: Shubhrajyoti Datta
---
drivers/clk/Kconfig | 6 +
drivers/clk/Makefile| 1 +
drivers/clk/clk-xlnx-clock-wizard.c | 335
3 files
From: Shubhrajyoti Datta
The patch adds support for dynamic reconfiguration of clock output rate.
Output clocks are registered as dividers and set rate callback function
is used for dynamic reconfiguration.
Based on the initial work from Chirag.
Signed-off-by: Chirag Parekh
Signed-off
On Mon, Sep 10, 2018 at 10:36 PM Greg Kroah-Hartman
wrote:
>
> On Mon, Sep 10, 2018 at 10:28:25PM +0530, Shubhrajyoti Datta wrote:
> > On Mon, Sep 10, 2018 at 2:41 PM Greg KH wrote:
> > >
> > > On Mon, Sep 10, 2018 at 10:47:28AM +0530, shubhrajyoti.da...@gmail.
On Mon, Sep 10, 2018 at 2:41 PM Greg KH wrote:
>
> On Mon, Sep 10, 2018 at 10:47:28AM +0530, shubhrajyoti.da...@gmail.com wrote:
> > From: Shubhrajyoti Datta
> >
> > The patch adds support for dynamic reconfiguration of clock output rate.
> > Output clocks are regis
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