[PATCH] stagin: clocking-wizard: Handle invalid clk in notifier

-wizard/clk-xlnx-clock-wizard.c:99:6: warning: 'max' >> may be used uninitialized in this function [-Wmaybe-uninitialized] if (ndata->new_rate > max) ^ Reported-by: kbuild test robot Signed-off-by: Soren Brinkmann --- drivers/staging/clocking-wizard/clk-xlnx-c

[PATCH] staging: clocking-wizard: Contain macro argument in parenthesis

A macro doing some arithmetic to calculate a register offset, did not contain an argument to the macro in parentheses, potentially leading to unexpected results when using that macro with arithmetic expressions as argument. Signed-off-by: Soren Brinkmann --- drivers/staging/clocking-wizard/clk

[PATCH v3] staging: Add Xilinx Clocking Wizard driver

Add a driver for the Xilinx Clocking Wizard soft IP. The clocking wizard provides an AXI interface to dynamically reconfigure the clocking resources of Xilinx FPGAs. Signed-off-by: Soren Brinkmann --- v3: - allow building the driver as module - make speed grade positive - document valid

[PATCH v2] staging: Add Xilinx Clocking Wizard driver

Add a driver for the Xilinx Clocking Wizard soft IP. The clocking wizard provides an AXI interface to dynamically reconfigure the clocking resources of Xilinx FPGAs. Signed-off-by: Soren Brinkmann --- Hi Greg, Dan, I fixed the things Dan pointed out, please take this v2 instead of the original

[PATCH] staging: Add Xilinx Clocking Wizard driver

Add a driver for the Xilinx Clocking Wizard soft IP. The clocking wizard provides an AXI interface to dynamically reconfigure the clocking resources of Xilinx FPGAs. Signed-off-by: Soren Brinkmann --- drivers/staging/Kconfig| 2 + drivers/staging/Makefile