Re: [PATCH 0/7] MIPS: ralink: add CPU clock detection and clock gate driver for MT7621

2020-11-12 Thread Sergio Paracuellos
On Fri, Nov 13, 2020 at 1:40 AM Chuanhong Guo wrote: > > On Thu, Nov 12, 2020 at 1:23 PM Sergio Paracuellos > wrote: > > > > To avoid weird behaviour because of some drivers are > > not using properly clocks we have the CLK_IGNORED_UNUSED, which as you > > can see is currently being used in my

Re: [PATCH 0/7] MIPS: ralink: add CPU clock detection and clock gate driver for MT7621

2020-11-12 Thread Chuanhong Guo
On Thu, Nov 12, 2020 at 1:23 PM Sergio Paracuellos wrote: > > To avoid weird behaviour because of some drivers are > not using properly clocks we have the CLK_IGNORED_UNUSED, which as you > can see is currently being used in my code. Using that all seems to > work as expected as it is now. The

Re: [PATCH 0/7] MIPS: ralink: add CPU clock detection and clock gate driver for MT7621

2020-11-11 Thread Sergio Paracuellos
Hi, On Thu, Nov 12, 2020 at 2:34 AM Chuanhong Guo wrote: > > On Thu, Nov 12, 2020 at 9:26 AM Chuanhong Guo wrote: > > > > I've already said in previous threads that clock assignment in > > current linux kernel is not trustworthy. > > I've got the clock plan for mt7621 now. (Can't share it,

Re: [PATCH 0/7] MIPS: ralink: add CPU clock detection and clock gate driver for MT7621

2020-11-11 Thread Sergio Paracuellos
Hi Chuanhong, On Thu, Nov 12, 2020 at 2:26 AM Chuanhong Guo wrote: [snip] > > I've already said in previous threads that clock assignment in > current linux kernel is not trustworthy. > I've got the clock plan for mt7621 now. (Can't share it, sorry.) > Most of your clock assumptions above are

Re: [PATCH 0/7] MIPS: ralink: add CPU clock detection and clock gate driver for MT7621

2020-11-11 Thread Chuanhong Guo
On Thu, Nov 12, 2020 at 9:26 AM Chuanhong Guo wrote: > > I've already said in previous threads that clock assignment in > current linux kernel is not trustworthy. > I've got the clock plan for mt7621 now. (Can't share it, sorry.) > Most of your clock assumptions above are incorrect. > I've made a

Re: [PATCH 0/7] MIPS: ralink: add CPU clock detection and clock gate driver for MT7621

2020-11-11 Thread Chuanhong Guo
Hi! On Thu, Nov 12, 2020 at 12:30 AM Sergio Paracuellos wrote: > > This patchset ports CPU clock detection for MT7621 from OpenWrt > and adds a complete clock plan for the mt7621 SOC. > > The documentation for this SOC only talks about two registers > regarding to the clocks: > *

[PATCH 0/7] MIPS: ralink: add CPU clock detection and clock gate driver for MT7621

2020-11-11 Thread Sergio Paracuellos
This patchset ports CPU clock detection for MT7621 from OpenWrt and adds a complete clock plan for the mt7621 SOC. The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and