* K. Y. Srinivasan k...@microsoft.com wrote:
If the hypervisor supports MSR based access to the APIC registers
(EOI, TPR and ICR), implement the MSR based access.
Signed-off-by: K. Y. Srinivasan k...@microsoft.com
---
Changes from V1: Addressed comments from Ingo Molnar
;
a...@canonical.com; jasow...@redhat.com; t...@linutronix.de;
h...@zytor.com
Subject: Re: [PATCH V2 1/1] X86: hyperv: Enable MSR based APIC access
* K. Y. Srinivasan k...@microsoft.com wrote:
If the hypervisor supports MSR based access to the APIC registers
(EOI, TPR and ICR
If the hypervisor supports MSR based access to the APIC registers
(EOI, TPR and ICR), implement the MSR based access.
Signed-off-by: K. Y. Srinivasan k...@microsoft.com
---
Changes from V1: Addressed comments from Ingo Molnar
mingo.kernel@gmail.com
arch/x86/kernel/cpu/mshyperv.c | 62
