If there is only one output then allow changing of the parent rate.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.da...@xilinx.com>
---
drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
index 9cc2f6d..e08fc2f 100644
--- a/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
+++ b/drivers/staging/clocking-wizard/clk-xlnx-clock-wizard.c
@@ -138,6 +138,7 @@ static int clk_wzrd_probe(struct platform_device *pdev)
void __iomem *ctrl_reg;
struct clk_wzrd *clk_wzrd;
struct device_node *np = pdev->dev.of_node;
+ int nr_outputs;
unsigned long flags = 0;
clk_wzrd = devm_kzalloc(&pdev->dev, sizeof(*clk_wzrd), GFP_KERNEL);
@@ -201,6 +202,14 @@ static int clk_wzrd_probe(struct platform_device *pdev)
goto err_disable_clk;
}
+ ret = of_property_read_u32(np, "nr-outputs", &nr_outputs);
+ if (ret || nr_outputs > WZRD_NUM_OUTPUTS) {
+ ret = -EINVAL;
+ goto err_disable_clk;
+ }
+ if (nr_outputs == 1)
+ flags = CLK_SET_RATE_PARENT;
+
clk_wzrd->clks_internal[wzrd_clk_mul] = clk_register_fixed_factor
(&pdev->dev, clk_name,
__clk_get_name(clk_wzrd->clk_in1),
--
2.1.1
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