set_pcie_phy can be refactor to use mt7621_pci_reg_write and
mt7621_pci_reg_read functions intead of use pointer arithmetics.
Use them and simplify implicated calls and definitions along the
code.
Signed-off-by: Sergio Paracuellos <sergio.paracuel...@gmail.com>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 122 ++++++++++++++++----------------
1 file changed, 62 insertions(+), 60 deletions(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c
b/drivers/staging/mt7621-pci/pci-mt7621.c
index 904181c..897485a 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -79,7 +79,6 @@
#define RALINK_PCI_PCIMSK_ADDR 0x000C
#define RALINK_PCI_BASE 0xBE140000
-#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
static u16 pcie_controller_offsets[] = {
0x2000, 0x3000, 0x4000,
@@ -95,8 +94,8 @@ static u16 pcie_controller_offsets[] = {
#define RALINK_PCI_ECRC(dev) (pcie_controller_offsets[(dev)] +
0x0064)
-#define RALINK_PCIEPHY_P0P1_CTL_OFFSET (RALINK_PCI_BASE + 0x9000)
-#define RALINK_PCIEPHY_P2_CTL_OFFSET (RALINK_PCI_BASE + 0xA000)
+#define RALINK_PCIEPHY_P0P1_CTL_OFFSET 0x9000
+#define RALINK_PCIEPHY_P2_CTL_OFFSET 0xA000
#define RALINK_PCI_MM_MAP_BASE 0x60000000
#define RALINK_PCI_IO_MAP_BASE 0x1e160000
@@ -289,24 +288,27 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8
pin)
}
void
-set_pcie_phy(u32 *addr, int start_b, int bits, int val)
+set_pcie_phy(u32 offset, int start_b, int bits, int val)
{
- *(unsigned int *)(addr) &= ~(((1<<bits) - 1)<<start_b);
- *(unsigned int *)(addr) |= val << start_b;
+ u32 reg = mt7621_pci_reg_read(offset);
+
+ reg &= ~(((1 << bits) - 1) << start_b);
+ reg |= val << start_b;
+ mt7621_pci_reg_write(reg, offset);
}
void
bypass_pipe_rst(void)
{
/* PCIe Port 0 */
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1,
0x01); // rg_pe1_pipe_rst_b
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 4, 1,
0x01); // rg_pe1_pipe_cmd_frc[4]
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 12, 1, 0x01);
// rg_pe1_pipe_rst_b
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x02c), 4, 1, 0x01);
// rg_pe1_pipe_cmd_frc[4]
/* PCIe Port 1 */
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1,
0x01); // rg_pe1_pipe_rst_b
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 4, 1,
0x01); // rg_pe1_pipe_cmd_frc[4]
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 12, 1, 0x01);
// rg_pe1_pipe_rst_b
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x12c), 4, 1, 0x01);
// rg_pe1_pipe_cmd_frc[4]
/* PCIe Port 2 */
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1,
0x01); // rg_pe1_pipe_rst_b
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 4, 1,
0x01); // rg_pe1_pipe_cmd_frc[4]
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 12, 1, 0x01);
// rg_pe1_pipe_rst_b
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x02c), 4, 1, 0x01);
// rg_pe1_pipe_cmd_frc[4]
}
void
@@ -317,77 +319,77 @@ set_phy_for_ssc(void)
reg = (reg >> 6) & 0x7;
/* Set PCIe Port0 & Port1 PHY to disable SSC */
/* Debug Xtal Type */
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1,
0x01); // rg_pe1_frc_h_xtal_type
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2,
0x00); // rg_pe1_h_xtal_type
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1,
0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1,
0x01); // rg_pe1_frc_phy_en //Force Port 1 enable control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1,
0x00); // rg_pe1_phy_en //Port 0 disable
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1,
0x00); // rg_pe1_phy_en //Port 1 disable
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 8, 1, 0x01);
// rg_pe1_frc_h_xtal_type
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x400), 9, 2, 0x00);
// rg_pe1_h_xtal_type
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x01);
// rg_pe1_frc_phy_en //Force Port 0 enable control
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x01);
// rg_pe1_frc_phy_en //Force Port 1 enable control
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x00);
// rg_pe1_phy_en //Port 0 disable
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x00);
// rg_pe1_phy_en //Port 1 disable
if (reg <= 5 && reg >= 3) { // 40MHz Xtal
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),
6, 2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2,
0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
printk("***** Xtal 40MHz *****\n");
} else { // 25MHz | 20MHz Xtal
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490),
6, 2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 6, 2,
0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
if (reg >= 6) {
printk("***** Xtal 25MHz *****\n");
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET +
0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET +
0x49c), 0, 31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO
PCW (for host mode)
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET +
0x4a4), 0, 16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither
period control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET +
0x4a8), 0, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither
amplitude control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET +
0x4a8), 16, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither
amplitude control for initial
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4bc),
4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x49c),
0, 31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for
host mode)
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a4),
0, 16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period control
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8),
0, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude
control
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a8),
16, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude
control for initial
} else {
printk("***** Xtal 20MHz *****\n");
}
}
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1,
0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2,
0x02); // RG_PE1_H_PLL_BC
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4,
0x06); // RG_PE1_H_PLL_BP
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4,
0x02); // RG_PE1_H_PLL_IR
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4,
0x01); // RG_PE1_H_PLL_IC
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3,
0x00); // RG_PE1_H_PLL_BR
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3,
0x02); // RG_PE1_PLL_DIVEN
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4a0), 5, 1, 0x01);
// RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 22, 2, 0x02);
// RG_PE1_H_PLL_BC
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 18, 4, 0x06);
// RG_PE1_H_PLL_BP
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 12, 4, 0x02);
// RG_PE1_H_PLL_IR
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 8, 4, 0x01);
// RG_PE1_H_PLL_IC
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x4ac), 16, 3, 0x00);
// RG_PE1_H_PLL_BR
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x490), 1, 3, 0x02);
// RG_PE1_PLL_DIVEN
if (reg <= 5 && reg >= 3) { // 40MHz Xtal
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),
6, 2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv
when force mode enable
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414),
5, 1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 6, 2,
0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when force
mode enable
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x414), 5, 1,
0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
}
/* Enable PHY and disable force mode */
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1,
0x01); // rg_pe1_phy_en //Port 0 enable
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1,
0x01); // rg_pe1_phy_en //Port 1 enable
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1,
0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1,
0x00); // rg_pe1_frc_phy_en //Force Port 1 disable control
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 5, 1, 0x01);
// rg_pe1_phy_en //Port 0 enable
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 5, 1, 0x01);
// rg_pe1_phy_en //Port 1 enable
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x000), 4, 1, 0x00);
// rg_pe1_frc_phy_en //Force Port 0 disable control
+ set_pcie_phy((RALINK_PCIEPHY_P0P1_CTL_OFFSET + 0x100), 4, 1, 0x00);
// rg_pe1_frc_phy_en //Force Port 1 disable control
/* Set PCIe Port2 PHY to disable SSC */
/* Debug Xtal Type */
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1,
0x01); // rg_pe1_frc_h_xtal_type
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2,
0x00); // rg_pe1_h_xtal_type
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1,
0x01); // rg_pe1_frc_phy_en //Force Port 0 enable control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1,
0x00); // rg_pe1_phy_en //Port 0 disable
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 8, 1, 0x01);
// rg_pe1_frc_h_xtal_type
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x400), 9, 2, 0x00);
// rg_pe1_h_xtal_type
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x01);
// rg_pe1_frc_phy_en //Force Port 0 enable control
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x00);
// rg_pe1_phy_en //Port 0 disable
if (reg <= 5 && reg >= 3) { // 40MHz Xtal
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6,
2, 0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2,
0x01); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
} else { // 25MHz | 20MHz Xtal
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6,
2, 0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 6, 2,
0x00); // RG_PE1_H_PLL_PREDIV //Pre-divider ratio (for host mode)
if (reg >= 6) { // 25MHz Xtal
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET +
0x4bc), 4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET +
0x49c), 0, 31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO
PCW (for host mode)
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET +
0x4a4), 0, 16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither
period control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET +
0x4a8), 0, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither
amplitude control
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET +
0x4a8), 16, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither
amplitude control for initial
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4bc),
4, 2, 0x01); // RG_PE1_H_PLL_FBKSEL //Feedback clock select
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x49c),
0, 31, 0x18000000); // RG_PE1_H_LCDDS_PCW_NCPO //DDS NCPO PCW (for
host mode)
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a4),
0, 16, 0x18d); // RG_PE1_H_LCDDS_SSC_PRD //DDS SSC dither period
control
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8),
0, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA //DDS SSC dither amplitude
control
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a8),
16, 12, 0x4a); // RG_PE1_H_LCDDS_SSC_DELTA1 //DDS SSC dither amplitude
control for initial
}
}
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1,
0x01); // RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2,
0x02); // RG_PE1_H_PLL_BC
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4,
0x06); // RG_PE1_H_PLL_BP
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4,
0x02); // RG_PE1_H_PLL_IR
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4,
0x01); // RG_PE1_H_PLL_IC
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3,
0x00); // RG_PE1_H_PLL_BR
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3,
0x02); // RG_PE1_PLL_DIVEN
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4a0), 5, 1, 0x01);
// RG_PE1_LCDDS_CLK_PH_INV //DDS clock inversion
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 22, 2, 0x02);
// RG_PE1_H_PLL_BC
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 18, 4, 0x06);
// RG_PE1_H_PLL_BP
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 12, 4, 0x02);
// RG_PE1_H_PLL_IR
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 8, 4, 0x01);
// RG_PE1_H_PLL_IC
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x4ac), 16, 3, 0x00);
// RG_PE1_H_PLL_BR
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x490), 1, 3, 0x02);
// RG_PE1_PLL_DIVEN
if (reg <= 5 && reg >= 3) { // 40MHz Xtal
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6,
2, 0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when
force mode enable
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5,
1, 0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 6, 2,
0x01); // rg_pe1_mstckdiv //value of da_pe1_mstckdiv when
force mode enable
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x414), 5, 1,
0x01); // rg_pe1_frc_mstckdiv //force mode enable of da_pe1_mstckdiv
}
/* Enable PHY and disable force mode */
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1,
0x01); // rg_pe1_phy_en //Port 0 enable
- set_pcie_phy((u32 *)(RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1,
0x00); // rg_pe1_frc_phy_en //Force Port 0 disable control
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 5, 1, 0x01);
// rg_pe1_phy_en //Port 0 enable
+ set_pcie_phy((RALINK_PCIEPHY_P2_CTL_OFFSET + 0x000), 4, 1, 0x00);
// rg_pe1_frc_phy_en //Force Port 0 disable control
}
void setup_cm_memory_region(struct resource *mem_resource)
--
2.7.4
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