Re: [PATCH v4 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

Hi all, On Sun, Nov 22, 2020 at 10:55 AM Sergio Paracuellos wrote: > > This patchset ports CPU clock detection for MT7621 from OpenWrt > and adds a complete clock plan for the mt7621 SOC. > > The documentation for this SOC only talks about two registers > regarding to the clocks: > * SYSC_REG_CPL

[PATCH v4 0/6] MIPS: ralink: add CPU clock detection and clock driver for MT7621

This patchset ports CPU clock detection for MT7621 from OpenWrt and adds a complete clock plan for the mt7621 SOC. The documentation for this SOC only talks about two registers regarding to the clocks: * SYSC_REG_CPLL_CLKCFG0 - provides some information about boostrapped refclock. PLL and dividers