On Mon, Mar 22, 2021 at 01:01:54PM +0200, Eli Billauer wrote:
> Hello, Greg.
>
> Thanks for your comments. I'd like to address a couple of them.
>
> First, there's the lockless FIFO that is implemented in the driver:
>
> On 21/03/21 14:23, Greg KH wrote:
> >
> > > +
> > > +static unsigned int f
Hello, Greg.
Thanks for your comments. I'd like to address a couple of them.
First, there's the lockless FIFO that is implemented in the driver:
On 21/03/21 14:23, Greg KH wrote:
+
+static unsigned int fifo_read(struct xillyfifo *fifo,
+ void *data, unsigned int l
On Thu, Mar 11, 2021 at 11:50:33AM +0200, eli.billa...@gmail.com wrote:
> From: Eli Billauer
>
> The XillyUSB driver is the USB variant for the Xillybus FPGA IP core.
> Even though it presents a nearly identical API on the FPGA and host,
> it's almost a complete rewrite of the driver: The framewo
From: Eli Billauer
The XillyUSB driver is the USB variant for the Xillybus FPGA IP core.
Even though it presents a nearly identical API on the FPGA and host,
it's almost a complete rewrite of the driver: The framework for exchanging
data on a USB bus is fundamentally different from doing the same
