Re: [patch 09/11] x86/vdso: Simplify the invalid vclock case

2018-09-27 Thread Thomas Gleixner
On Tue, 18 Sep 2018, Thomas Gleixner wrote: > On Tue, 18 Sep 2018, Thomas Gleixner wrote: > > So if the TSC on CPU1 is slightly behind the TSC on CPU0 then now1 can be > > smaller than cycle_last. The TSC sync stuff does not catch the small delta > > for unknown raisins. I'll go and find that

Re: [patch 09/11] x86/vdso: Simplify the invalid vclock case

2018-09-27 Thread Andy Lutomirski
> On Sep 27, 2018, at 7:36 AM, Thomas Gleixner wrote: > >> On Wed, 19 Sep 2018, Thomas Gleixner wrote: >> On Tue, 18 Sep 2018, Andy Lutomirski wrote: On Sep 18, 2018, at 3:46 PM, Thomas Gleixner wrote: > On Tue, 18 Sep 2018, Andy Lutomirski wrote: > Do we do better if we use

Re: [patch 09/11] x86/vdso: Simplify the invalid vclock case

2018-09-27 Thread Thomas Gleixner
On Wed, 19 Sep 2018, Thomas Gleixner wrote: > On Tue, 18 Sep 2018, Andy Lutomirski wrote: > > > On Sep 18, 2018, at 3:46 PM, Thomas Gleixner wrote: > > > On Tue, 18 Sep 2018, Andy Lutomirski wrote: > > >> Do we do better if we use signed arithmetic for the whole calculation? > > >> Then a small

Re: [patch 09/11] x86/vdso: Simplify the invalid vclock case

2018-09-19 Thread Thomas Gleixner
On Wed, 19 Sep 2018, Rasmus Villemoes wrote: > On 2018-09-19 00:46, Thomas Gleixner wrote: > > On Tue, 18 Sep 2018, Andy Lutomirski wrote: > >>> > >> > >> Do we do better if we use signed arithmetic for the whole calculation? > >> Then a small backwards movement would result in a small backwards

Re: [patch 09/11] x86/vdso: Simplify the invalid vclock case

2018-09-19 Thread Rasmus Villemoes
On 2018-09-19 00:46, Thomas Gleixner wrote: > On Tue, 18 Sep 2018, Andy Lutomirski wrote: >>> >> >> Do we do better if we use signed arithmetic for the whole calculation? >> Then a small backwards movement would result in a small backwards result. >> Or we could offset everything so that we’d have

Re: [patch 09/11] x86/vdso: Simplify the invalid vclock case

2018-09-18 Thread Thomas Gleixner
On Tue, 18 Sep 2018, Andy Lutomirski wrote: > > On Sep 18, 2018, at 3:46 PM, Thomas Gleixner wrote: > > On Tue, 18 Sep 2018, Andy Lutomirski wrote: > >> Do we do better if we use signed arithmetic for the whole calculation? > >> Then a small backwards movement would result in a small backwards

Re: [patch 09/11] x86/vdso: Simplify the invalid vclock case

2018-09-18 Thread Andy Lutomirski
> On Sep 18, 2018, at 3:46 PM, Thomas Gleixner wrote: > > On Tue, 18 Sep 2018, Andy Lutomirski wrote: >>> On Sep 18, 2018, at 12:52 AM, Thomas Gleixner wrote: >>> > On Mon, 17 Sep 2018, John Stultz wrote: > On Mon, Sep 17, 2018 at 12:25 PM, Andy Lutomirski wrote: > Also, I'm not

Re: [patch 09/11] x86/vdso: Simplify the invalid vclock case

2018-09-18 Thread Thomas Gleixner
On Tue, 18 Sep 2018, Andy Lutomirski wrote: > > On Sep 18, 2018, at 12:52 AM, Thomas Gleixner wrote: > > > >> On Mon, 17 Sep 2018, John Stultz wrote: > >>> On Mon, Sep 17, 2018 at 12:25 PM, Andy Lutomirski wrote: > >>> Also, I'm not entirely convinced that this "last" thing is needed at > >>>

Re: [patch 09/11] x86/vdso: Simplify the invalid vclock case

2018-09-18 Thread Thomas Gleixner
On Tue, 18 Sep 2018, Thomas Gleixner wrote: > So if the TSC on CPU1 is slightly behind the TSC on CPU0 then now1 can be > smaller than cycle_last. The TSC sync stuff does not catch the small delta > for unknown raisins. I'll go and find that machine and test that again. Of course it does not

Re: [patch 09/11] x86/vdso: Simplify the invalid vclock case

2018-09-18 Thread Andy Lutomirski
> On Sep 18, 2018, at 12:52 AM, Thomas Gleixner wrote: > >> On Mon, 17 Sep 2018, John Stultz wrote: >>> On Mon, Sep 17, 2018 at 12:25 PM, Andy Lutomirski wrote: >>> Also, I'm not entirely convinced that this "last" thing is needed at >>> all. John, what's the scenario under which we need it?

Re: [patch 09/11] x86/vdso: Simplify the invalid vclock case

2018-09-18 Thread Peter Zijlstra
On Tue, Sep 18, 2018 at 03:23:08PM +0200, Thomas Gleixner wrote: > On Tue, 18 Sep 2018, Peter Zijlstra wrote: > > On Tue, Sep 18, 2018 at 12:41:57PM +0200, Thomas Gleixner wrote: > > > I still have one of the machines which is affected by this. > > > > Are we sure this isn't a load vs rdtsc

Re: [patch 09/11] x86/vdso: Simplify the invalid vclock case

2018-09-18 Thread Thomas Gleixner
On Tue, 18 Sep 2018, Peter Zijlstra wrote: > On Tue, Sep 18, 2018 at 12:41:57PM +0200, Thomas Gleixner wrote: > > I still have one of the machines which is affected by this. > > Are we sure this isn't a load vs rdtsc reorder? Because if I look at the > current code: The load order of last vs.

Re: [patch 09/11] x86/vdso: Simplify the invalid vclock case

2018-09-18 Thread Peter Zijlstra
On Tue, Sep 18, 2018 at 12:41:57PM +0200, Thomas Gleixner wrote: > On Tue, 18 Sep 2018, Thomas Gleixner wrote: > > On Tue, 18 Sep 2018, Thomas Gleixner wrote: > > > On Tue, 18 Sep 2018, Peter Zijlstra wrote: > > > > > Your memory serves you right. That's indeed observable on CPUs which > > > > >

Re: [patch 09/11] x86/vdso: Simplify the invalid vclock case

2018-09-18 Thread Thomas Gleixner
On Tue, 18 Sep 2018, Thomas Gleixner wrote: > On Tue, 18 Sep 2018, Thomas Gleixner wrote: > > On Tue, 18 Sep 2018, Peter Zijlstra wrote: > > > > Your memory serves you right. That's indeed observable on CPUs which > > > > lack TSC_ADJUST. > > > > > > But, if the gtod code can observe this, then

Re: [patch 09/11] x86/vdso: Simplify the invalid vclock case

2018-09-18 Thread Thomas Gleixner
On Tue, 18 Sep 2018, Thomas Gleixner wrote: > On Tue, 18 Sep 2018, Peter Zijlstra wrote: > > > Your memory serves you right. That's indeed observable on CPUs which > > > lack TSC_ADJUST. > > > > But, if the gtod code can observe this, then why doesn't the code that > > checks the sync? > >

Re: [patch 09/11] x86/vdso: Simplify the invalid vclock case

2018-09-18 Thread Thomas Gleixner
On Tue, 18 Sep 2018, Peter Zijlstra wrote: > On Tue, Sep 18, 2018 at 09:52:26AM +0200, Thomas Gleixner wrote: > > On Mon, 17 Sep 2018, John Stultz wrote: > > > On Mon, Sep 17, 2018 at 12:25 PM, Andy Lutomirski wrote: > > > > Also, I'm not entirely convinced that this "last" thing is needed at > >

Re: [patch 09/11] x86/vdso: Simplify the invalid vclock case

2018-09-18 Thread Peter Zijlstra
On Tue, Sep 18, 2018 at 09:52:26AM +0200, Thomas Gleixner wrote: > On Mon, 17 Sep 2018, John Stultz wrote: > > On Mon, Sep 17, 2018 at 12:25 PM, Andy Lutomirski wrote: > > > Also, I'm not entirely convinced that this "last" thing is needed at > > > all. John, what's the scenario under which we

Re: [patch 09/11] x86/vdso: Simplify the invalid vclock case

2018-09-18 Thread Thomas Gleixner
On Mon, 17 Sep 2018, John Stultz wrote: > On Mon, Sep 17, 2018 at 12:25 PM, Andy Lutomirski wrote: > > Also, I'm not entirely convinced that this "last" thing is needed at > > all. John, what's the scenario under which we need it? > > So my memory is probably a bit foggy, but I recall that as

Re: [patch 09/11] x86/vdso: Simplify the invalid vclock case

2018-09-17 Thread John Stultz
On Mon, Sep 17, 2018 at 12:25 PM, Andy Lutomirski wrote: > On Fri, Sep 14, 2018 at 5:50 AM, Thomas Gleixner wrote: >> The code flow for the vclocks is convoluted as it requires the vclocks >> which can be invalidated separately from the vsyscall_gtod_data sequence to >> store the fact in a

Re: [patch 09/11] x86/vdso: Simplify the invalid vclock case

2018-09-17 Thread Andy Lutomirski
On Fri, Sep 14, 2018 at 5:50 AM, Thomas Gleixner wrote: > The code flow for the vclocks is convoluted as it requires the vclocks > which can be invalidated separately from the vsyscall_gtod_data sequence to > store the fact in a separate variable. That's inefficient. > > notrace static int

[patch 09/11] x86/vdso: Simplify the invalid vclock case

2018-09-14 Thread Thomas Gleixner
The code flow for the vclocks is convoluted as it requires the vclocks which can be invalidated separately from the vsyscall_gtod_data sequence to store the fact in a separate variable. That's inefficient. Restructure the code so the vclock readout returns cycles and the conversion to nanoseconds