On Tue, 2012-05-29 at 23:25 +0900, Hiroaki SHIMODA wrote: > If I understand the code and spec correctly, TX interrupts are > generated when TXDCTL.WTHRESH descriptors have been accumulated > and write backed. > > I tentatively changed the TXDCTL.WTHRESH to 1, then it seems > that latency spikes are disappear. > > drivers/net/ethernet/intel/e1000e/e1000.h > @@ -181,7 +181,7 @@ struct e1000_info; > #define E1000_TXDCTL_DMA_BURST_ENABLE \ > (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \ > E1000_TXDCTL_COUNT_DESC | \ > - (5 << 16) | /* wthresh must be +1 more than desired */\ > + (1 << 16) | /* wthresh must be +1 more than desired */\ > (1 << 8) | /* hthresh */ \ > 0x1f) /* pthresh */ >
I just want to add that this patch helped with the problem on my system as well. I found that before, packets were left in the buffer instead of being sent out as expected, as show with pings. On a i5(2400) H67 system with: 02:00.0 Ethernet controller: Intel Corporation 82571EB Gigabit Ethernet Controller (rev 06) 02:00.1 Ethernet controller: Intel Corporation 82571EB Gigabit Ethernet Controller (rev 06) Thanks! ------------------------------------------------------------------------------ Live Security Virtual Conference Exclusive live event will cover all the ways today's security and threat landscape has changed and how IT managers can respond. Discussions will include endpoint security, mobile security and the latest in malware threats. http://www.accelacomm.com/jaw/sfrnl04242012/114/50122263/ _______________________________________________ E1000-devel mailing list E1000-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/e1000-devel To learn more about Intel® Ethernet, visit http://communities.intel.com/community/wired
